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Message-ID: <20240717114155.1a3d4c07@canb.auug.org.au>
Date: Wed, 17 Jul 2024 11:41:55 +1000
From: Stephen Rothwell <sfr@...b.auug.org.au>
To: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>, Peter Zijlstra <peterz@...radead.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>
Cc: "Borislav Petkov (AMD)" <bp@...en8.de>, Linux Kernel Mailing List
<linux-kernel@...r.kernel.org>, Linux Next Mailing List
<linux-next@...r.kernel.org>, Mario Limonciello
<mario.limonciello@....com>, Perry Yuan <perry.yuan@....com>, "Rafael J.
Wysocki" <rafael.j.wysocki@...el.com>, Srinivas Pandruvada
<srinivas.pandruvada@...ux.intel.com>, Xiaojian Du <Xiaojian.Du@....com>
Subject: Re: linux-next: manual merge of the tip tree with the pm tree
Hi all,
On Tue, 2 Jul 2024 14:15:55 +1000 Stephen Rothwell <sfr@...b.auug.org.au> wrote:
>
> Today's linux-next merge of the tip tree got a conflict in:
>
> arch/x86/include/asm/cpufeatures.h
>
> between commits:
>
> c7107750b2ff ("x86/cpufeatures: Add AMD FAST CPPC feature flag")
> 7ea81936b853 ("x86/cpufeatures: Add HWP highest perf change feature flag")
>
> from the pm tree and commit:
>
> 78ce84b9e0a5 ("x86/cpufeatures: Flip the /proc/cpuinfo appearance logic")
>
> from the tip tree.
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging. You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc arch/x86/include/asm/cpufeatures.h
> index 0d99515530d3,6007462e03d6..000000000000
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@@ -283,90 -283,89 +283,90 @@@
> *
> * Reuse free bits when adding new feature flags!
> */
> - #define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
> - #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
> - #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
> - #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
> - #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
> - #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
> - #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
> - #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
> - #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */
> - #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */
> - #define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */
> - #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */
> - #define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
> - #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
> - #define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
> - #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
> - #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
> - #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
> - #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
> - #define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
> - #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
> - #define X86_FEATURE_SMBA (11*32+21) /* "" Slow Memory Bandwidth Allocation */
> - #define X86_FEATURE_BMEC (11*32+22) /* "" Bandwidth Monitoring Event Configuration */
> - #define X86_FEATURE_USER_SHSTK (11*32+23) /* Shadow stack support for user mode applications */
> - #define X86_FEATURE_SRSO (11*32+24) /* "" AMD BTB untrain RETs */
> - #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
> - #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* "" Issue an IBPB only on VMEXIT */
> - #define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
> - #define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
> - #define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
> - #define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
> - #define X86_FEATURE_ZEN1 (11*32+31) /* "" CPU based on Zen1 microarchitecture */
> + #define X86_FEATURE_CQM_LLC (11*32+ 0) /* "cqm_llc" LLC QoS if 1 */
> + #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* "cqm_occup_llc" LLC occupancy monitoring */
> + #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* "cqm_mbm_total" LLC Total MBM monitoring */
> + #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* "cqm_mbm_local" LLC Local MBM monitoring */
> + #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* LFENCE in user entry SWAPGS path */
> + #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* LFENCE in kernel entry SWAPGS path */
> + #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* "split_lock_detect" #AC for split lock */
> + #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* Per-thread Memory Bandwidth Allocation */
> + #define X86_FEATURE_SGX1 (11*32+ 8) /* Basic SGX */
> + #define X86_FEATURE_SGX2 (11*32+ 9) /* SGX Enclave Dynamic Memory Management (EDMM) */
> + #define X86_FEATURE_ENTRY_IBPB (11*32+10) /* Issue an IBPB on kernel entry */
> + #define X86_FEATURE_RRSBA_CTRL (11*32+11) /* RET prediction control */
> + #define X86_FEATURE_RETPOLINE (11*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
> + #define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* Use LFENCE for Spectre variant 2 */
> + #define X86_FEATURE_RETHUNK (11*32+14) /* Use REturn THUNK */
> + #define X86_FEATURE_UNRET (11*32+15) /* AMD BTB untrain return */
> + #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* Use IBPB during runtime firmware calls */
> + #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* Fill RSB on VM exit when EIBRS is enabled */
> + #define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* SGX EDECCSSA user leaf function */
> + #define X86_FEATURE_CALL_DEPTH (11*32+19) /* Call depth tracking for RSB stuffing */
> + #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* MSR IA32_TSX_CTRL (Intel) implemented */
> + #define X86_FEATURE_SMBA (11*32+21) /* Slow Memory Bandwidth Allocation */
> + #define X86_FEATURE_BMEC (11*32+22) /* Bandwidth Monitoring Event Configuration */
> + #define X86_FEATURE_USER_SHSTK (11*32+23) /* "user_shstk" Shadow stack support for user mode applications */
> + #define X86_FEATURE_SRSO (11*32+24) /* AMD BTB untrain RETs */
> + #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* AMD BTB untrain RETs through aliasing */
> + #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* Issue an IBPB only on VMEXIT */
> + #define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
> + #define X86_FEATURE_ZEN2 (11*32+28) /* CPU based on Zen2 microarchitecture */
> + #define X86_FEATURE_ZEN3 (11*32+29) /* CPU based on Zen3 microarchitecture */
> + #define X86_FEATURE_ZEN4 (11*32+30) /* CPU based on Zen4 microarchitecture */
> + #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */
>
> /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> - #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
> - #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
> - #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
> - #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */
> - #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */
> - #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */
> - #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */
> - #define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */
> - #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */
> - #define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-serializing WRMSR */
> - #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
> - #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
> - #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */
> + #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
> + #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
> + #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */
> + #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural PerfMon Extension */
> + #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
> + #define X86_FEATURE_FSRS (12*32+11) /* Fast short REP STOSB */
> + #define X86_FEATURE_FSRC (12*32+12) /* Fast short REP {CMPSB,SCASB} */
> + #define X86_FEATURE_FRED (12*32+17) /* "fred" Flexible Return and Event Delivery */
> + #define X86_FEATURE_LKGS (12*32+18) /* Load "kernel" (userspace) GS */
> + #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */
> + #define X86_FEATURE_AMX_FP16 (12*32+21) /* AMX fp16 Support */
> + #define X86_FEATURE_AVX_IFMA (12*32+23) /* Support for VPMADD52[H,L]UQ */
> + #define X86_FEATURE_LAM (12*32+26) /* "lam" Linear Address Masking */
>
> /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
> - #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
> - #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
> - #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
> - #define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */
> - #define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
> - #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
> - #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
> - #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
> - #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
> - #define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */
> - #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
> - #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
> - #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
> - #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
> - #define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */
> - #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
> - #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
> + #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */
> + #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */
> + #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
> + #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */
> + #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
> + #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
> + #define X86_FEATURE_AMD_IBRS (13*32+14) /* Indirect Branch Restricted Speculation */
> + #define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
> + #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
> + #define X86_FEATURE_AMD_PPIN (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
> + #define X86_FEATURE_AMD_SSBD (13*32+24) /* Speculative Store Bypass Disable */
> + #define X86_FEATURE_VIRT_SSBD (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
> + #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* Speculative Store Bypass is fixed in hardware. */
> + #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */
> + #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */
> + #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */
> + #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */
>
> /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
> - #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
> - #define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
> - #define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
> - #define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
> - #define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
> - #define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
> - #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
> - #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
> - #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
> - #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
> - #define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* "" HWP Highest perf change */
> - #define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */
> + #define X86_FEATURE_DTHERM (14*32+ 0) /* "dtherm" Digital Thermal Sensor */
> + #define X86_FEATURE_IDA (14*32+ 1) /* "ida" Intel Dynamic Acceleration */
> + #define X86_FEATURE_ARAT (14*32+ 2) /* "arat" Always Running APIC Timer */
> + #define X86_FEATURE_PLN (14*32+ 4) /* "pln" Intel Power Limit Notification */
> + #define X86_FEATURE_PTS (14*32+ 6) /* "pts" Intel Package Thermal Status */
> + #define X86_FEATURE_HWP (14*32+ 7) /* "hwp" Intel Hardware P-states */
> + #define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* "hwp_notify" HWP Notification */
> + #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* "hwp_act_window" HWP Activity Window */
> + #define X86_FEATURE_HWP_EPP (14*32+10) /* "hwp_epp" HWP Energy Perf. Preference */
> + #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* "hwp_pkg_req" HWP Package Level Request */
> ++#define X86_FEATURE_HWP_HIGHEST_PERF_CHANGE (14*32+15) /* HWP Highest perf change */
> + #define X86_FEATURE_HFI (14*32+19) /* "hfi" Hardware Feedback Interface */
>
> /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
> - #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
> - #define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
> + #define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */
> + #define X86_FEATURE_LBRV (15*32+ 1) /* "lbrv" LBR Virtualization support */
> #define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
> #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
> #define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
> @@@ -466,12 -466,11 +467,12 @@@
> *
> * Reuse free bits when adding new feature flags!
> */
> - #define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */
> - #define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */
> - #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */
> - #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */
> - #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
> - #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */
> + #define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* "amd_lbr_pmc_freeze" AMD LBR and PMC Freeze */
> + #define X86_FEATURE_CLEAR_BHB_LOOP (21*32+ 1) /* Clear branch history at syscall entry using SW loop */
> + #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */
> + #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */
> + #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
> ++#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */
>
> /*
> * BUG word(s)
This is now a conflict between the pm tree and Linus' tree.
--
Cheers,
Stephen Rothwell
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