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Message-ID: <CAJ9a7Vg4YF-frWF2VNvhL-qyHp2wBaVD7TxzW=QG-LsUMKutHQ@mail.gmail.com>
Date: Wed, 17 Jul 2024 16:03:51 +0100
From: Mike Leach <mike.leach@...aro.org>
To: James Clark <james.clark@...aro.org>
Cc: coresight@...ts.linaro.org, suzuki.poulose@....com,
gankulkarni@...amperecomputing.com, leo.yan@...ux.dev,
anshuman.khandual@....com, James Clark <james.clark@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>,
John Garry <john.g.garry@...cle.com>, Will Deacon <will@...nel.org>,
Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>, Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>, "Liang, Kan" <kan.liang@...ux.intel.com>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com, linux-perf-users@...r.kernel.org
Subject: Re: [PATCH v5 17/17] coresight: Make trace ID map spinlock local to
the map
Reviewed-by: Mike Leach <mike.leach@...aro.org>
On Fri, 12 Jul 2024 at 11:23, James Clark <james.clark@...aro.org> wrote:
>
> From: James Clark <james.clark@....com>
>
> Reduce contention on the lock by replacing the global lock with one for
> each map.
>
> Signed-off-by: James Clark <james.clark@....com>
> Signed-off-by: James Clark <james.clark@...aro.org>
> ---
> drivers/hwtracing/coresight/coresight-core.c | 1 +
> .../hwtracing/coresight/coresight-trace-id.c | 26 +++++++++----------
> include/linux/coresight.h | 1 +
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index c427e9344a84..ea38ecf26fcb 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -1164,6 +1164,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc)
>
> if (csdev->type == CORESIGHT_DEV_TYPE_SINK ||
> csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) {
> + spin_lock_init(&csdev->perf_sink_id_map.lock);
> csdev->perf_sink_id_map.cpu_map = alloc_percpu(atomic_t);
> if (!csdev->perf_sink_id_map.cpu_map) {
> kfree(csdev);
> diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c
> index bddaed3e5cf8..d98e12cb30ec 100644
> --- a/drivers/hwtracing/coresight/coresight-trace-id.c
> +++ b/drivers/hwtracing/coresight/coresight-trace-id.c
> @@ -15,12 +15,10 @@
> /* Default trace ID map. Used in sysfs mode and for system sources */
> static DEFINE_PER_CPU(atomic_t, id_map_default_cpu_ids) = ATOMIC_INIT(0);
> static struct coresight_trace_id_map id_map_default = {
> - .cpu_map = &id_map_default_cpu_ids
> + .cpu_map = &id_map_default_cpu_ids,
> + .lock = __SPIN_LOCK_UNLOCKED(id_map_default.lock)
> };
>
> -/* lock to protect id_map and cpu data */
> -static DEFINE_SPINLOCK(id_map_lock);
> -
> /* #define TRACE_ID_DEBUG 1 */
> #if defined(TRACE_ID_DEBUG) || defined(CONFIG_COMPILE_TEST)
>
> @@ -123,11 +121,11 @@ static void coresight_trace_id_release_all(struct coresight_trace_id_map *id_map
> unsigned long flags;
> int cpu;
>
> - spin_lock_irqsave(&id_map_lock, flags);
> + spin_lock_irqsave(&id_map->lock, flags);
> bitmap_zero(id_map->used_ids, CORESIGHT_TRACE_IDS_MAX);
> for_each_possible_cpu(cpu)
> atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0);
> - spin_unlock_irqrestore(&id_map_lock, flags);
> + spin_unlock_irqrestore(&id_map->lock, flags);
> DUMP_ID_MAP(id_map);
> }
>
> @@ -136,7 +134,7 @@ static int _coresight_trace_id_get_cpu_id(int cpu, struct coresight_trace_id_map
> unsigned long flags;
> int id;
>
> - spin_lock_irqsave(&id_map_lock, flags);
> + spin_lock_irqsave(&id_map->lock, flags);
>
> /* check for existing allocation for this CPU */
> id = _coresight_trace_id_read_cpu_id(cpu, id_map);
> @@ -163,7 +161,7 @@ static int _coresight_trace_id_get_cpu_id(int cpu, struct coresight_trace_id_map
> atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), id);
>
> get_cpu_id_out_unlock:
> - spin_unlock_irqrestore(&id_map_lock, flags);
> + spin_unlock_irqrestore(&id_map->lock, flags);
>
> DUMP_ID_CPU(cpu, id);
> DUMP_ID_MAP(id_map);
> @@ -180,12 +178,12 @@ static void _coresight_trace_id_put_cpu_id(int cpu, struct coresight_trace_id_ma
> if (!id)
> return;
>
> - spin_lock_irqsave(&id_map_lock, flags);
> + spin_lock_irqsave(&id_map->lock, flags);
>
> coresight_trace_id_free(id, id_map);
> atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0);
>
> - spin_unlock_irqrestore(&id_map_lock, flags);
> + spin_unlock_irqrestore(&id_map->lock, flags);
> DUMP_ID_CPU(cpu, id);
> DUMP_ID_MAP(id_map);
> }
> @@ -195,10 +193,10 @@ static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *i
> unsigned long flags;
> int id;
>
> - spin_lock_irqsave(&id_map_lock, flags);
> + spin_lock_irqsave(&id_map->lock, flags);
> /* prefer odd IDs for system components to avoid legacy CPU IDS */
> id = coresight_trace_id_alloc_new_id(id_map, 0, true);
> - spin_unlock_irqrestore(&id_map_lock, flags);
> + spin_unlock_irqrestore(&id_map->lock, flags);
>
> DUMP_ID(id);
> DUMP_ID_MAP(id_map);
> @@ -209,9 +207,9 @@ static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map *
> {
> unsigned long flags;
>
> - spin_lock_irqsave(&id_map_lock, flags);
> + spin_lock_irqsave(&id_map->lock, flags);
> coresight_trace_id_free(id, id_map);
> - spin_unlock_irqrestore(&id_map_lock, flags);
> + spin_unlock_irqrestore(&id_map->lock, flags);
>
> DUMP_ID(id);
> DUMP_ID_MAP(id_map);
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 197949fd2c35..c13342594278 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -233,6 +233,7 @@ struct coresight_trace_id_map {
> DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
> atomic_t __percpu *cpu_map;
> atomic_t perf_cs_etm_session_active;
> + spinlock_t lock;
> };
>
> /**
> --
> 2.34.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
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