linux-kernel - [PATCH] ASoC: sof: amd: fix for firmware reload failure in Vangogh platform

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Message-ID: <20240718062004.581685-1-venkataprasad.potturu@amd.com>
Date: Thu, 18 Jul 2024 11:50:02 +0530
From: Venkata Prasad Potturu <venkataprasad.potturu@....com>
To: <broonie@...nel.org>, <alsa-devel@...a-project.org>
CC: <Vijendar.Mukunda@....com>, <Basavaraj.Hiregoudar@....com>,
	<Sunil-kumar.Dommati@....com>, <syed.sabakareem@....com>, "Venkata Prasad
 Potturu" <venkataprasad.potturu@....com>, Pierre-Louis Bossart
	<pierre-louis.bossart@...ux.intel.com>, Liam Girdwood <lgirdwood@...il.com>,
	Peter Ujfalusi <peter.ujfalusi@...ux.intel.com>, Bard Liao
	<yung-chuan.liao@...ux.intel.com>, Ranjani Sridharan
	<ranjani.sridharan@...ux.intel.com>, Daniel Baluta <daniel.baluta@....com>,
	Kai Vehmanen <kai.vehmanen@...ux.intel.com>, Jaroslav Kysela
	<perex@...ex.cz>, Takashi Iwai <tiwai@...e.com>, "moderated list:SOUND -
 SOUND OPEN FIRMWARE (SOF) DRIVERS" <sound-open-firmware@...a-project.org>,
	"open list:SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEM..."
	<linux-sound@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>
Subject: [PATCH] ASoC: sof: amd: fix for firmware reload failure in Vangogh platform

Setting ACP ACLK as clock source when ACP enters D0 state causing
firmware load failure, as per design clock source should be internal
clock.

Remove acp_clkmux_sel field so that ACP will use internal clock
source when ACP enters into D0 state.

Fixes: d0dab6b76a9f ("ASoC: SOF: amd: Add sof support for vangogh platform")

Signed-off-by: Venkata Prasad Potturu <venkataprasad.potturu@....com>
---
 sound/soc/sof/amd/pci-vangogh.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sound/soc/sof/amd/pci-vangogh.c b/sound/soc/sof/amd/pci-vangogh.c
index 16eb2994fbab..eba580840100 100644
--- a/sound/soc/sof/amd/pci-vangogh.c
+++ b/sound/soc/sof/amd/pci-vangogh.c
@@ -34,7 +34,6 @@ static const struct sof_amd_acp_desc vangogh_chip_info = {
 	.dsp_intr_base	= ACP5X_DSP_SW_INTR_BASE,
 	.sram_pte_offset = ACP5X_SRAM_PTE_OFFSET,
 	.hw_semaphore_offset = ACP5X_AXI2DAGB_SEM_0,
-	.acp_clkmux_sel = ACP5X_CLKMUX_SEL,
 	.probe_reg_offset = ACP5X_FUTURE_REG_ACLK_0,
 };
 
-- 
2.39.2