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Message-ID: <CALE0LRuKN0fPAJX+StBn+_N0L1-MvEoVGng+8miXuEDB7uEDpw@mail.gmail.com>
Date: Thu, 18 Jul 2024 12:28:25 +0200
From: Enric Balletbo i Serra <eballetb@...hat.com>
To: Siddharth Vadapalli <s-vadapalli@...com>
Cc: vkoul@...nel.org, kishon@...nel.org, sjakhade@...ence.com,
rogerq@...nel.org, thomas.richard@...tlin.com, robh@...nel.org,
linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH 1/2] phy: cadence-torrent: Add PCIe multilink
configuration for 100MHz refclk
Hi,
Many thanks for your patch. I'm not an expert on this but from a
general overview the patch looks good to me, for what it's worth I
picked the patches on my AM69-SK board and make it run USB and the
NVMe without problems so,
On Sat, Jun 15, 2024 at 11:35 AM Siddharth Vadapalli <s-vadapalli@...com> wrote:
>
> From: Swapnil Jakhade <sjakhade@...ence.com>
>
> Add register sequences to support PCIe multilink configuration for 100MHz
> reference clock. Maximum two PCIe links are supported.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@...ence.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
Tested-by: Enric Balletbo i Serra <eballetbo@...hat.com>
> ---
> drivers/phy/cadence/phy-cadence-torrent.c | 130 +++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 89e647bff99f..db60faeea988 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -197,6 +197,7 @@
> #define RX_SDCAL1_INIT_TMR 0x004CU
> #define RX_SDCAL1_ITER_TMR 0x004DU
> #define RX_CDRLF_CNFG 0x0080U
> +#define RX_CDRLF_CNFG2 0x0081U
> #define RX_CDRLF_CNFG3 0x0082U
> #define RX_SIGDET_HL_FILT_TMR 0x0090U
> #define RX_REE_GCSM1_CTRL 0x0108U
> @@ -204,6 +205,7 @@
> #define RX_REE_GCSM1_EQENM_PH2 0x010AU
> #define RX_REE_GCSM2_CTRL 0x0110U
> #define RX_REE_PERGCSM_CTRL 0x0118U
> +#define RX_REE_PEAK_UTHR 0x0142U
> #define RX_REE_ATTEN_THR 0x0149U
> #define RX_REE_TAP1_CLIP 0x0171U
> #define RX_REE_TAP2TON_CLIP 0x0172U
> @@ -212,6 +214,7 @@
> #define RX_DIAG_DFE_CTRL 0x01E0U
> #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
> #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
> +#define RX_DIAG_REE_DAC_CTRL 0x01E4U
> #define RX_DIAG_NQST_CTRL 0x01E5U
> #define RX_DIAG_SIGDET_TUNE 0x01E8U
> #define RX_DIAG_PI_RATE 0x01F4U
> @@ -3075,6 +3078,101 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
> cdns_torrent_clk_cleanup(cdns_phy);
> }
>
> +/* Multi link PCIe configuration */
> +static struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
> + {0x0002, PHY_PLL_CFG},
> + {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
> +};
> +
> +static struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
> + {0x0100, XCVR_DIAG_HSCLK_SEL},
> + {0x0001, XCVR_DIAG_HSCLK_DIV},
> + {0x0812, XCVR_DIAG_PLLDRC_CTRL}
> +};
> +
> +static struct cdns_torrent_vals ml_pcie_link_cmn_vals = {
> + .reg_pairs = ml_pcie_link_cmn_regs,
> + .num_regs = ARRAY_SIZE(ml_pcie_link_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals ml_pcie_xcvr_diag_ln_vals = {
> + .reg_pairs = ml_pcie_xcvr_diag_ln_regs,
> + .num_regs = ARRAY_SIZE(ml_pcie_xcvr_diag_ln_regs),
> +};
> +
> +/* Multi link PCIe, 100 MHz Ref clk, no SSC */
> +static struct cdns_reg_pairs ml_pcie_100_no_ssc_cmn_regs[] = {
> + {0x0003, CMN_PLL0_VCOCAL_TCTRL},
> + {0x0003, CMN_PLL1_VCOCAL_TCTRL}
> +};
> +
> +static struct cdns_reg_pairs ml_pcie_100_no_ssc_rx_ln_regs[] = {
> + {0x0019, RX_REE_TAP1_CLIP},
> + {0x0019, RX_REE_TAP2TON_CLIP},
> + {0x0008, RX_REE_PEAK_UTHR},
> + {0x018E, RX_CDRLF_CNFG},
> + {0x2E33, RX_CDRLF_CNFG2},
> + {0x0001, RX_DIAG_ACYA},
> + {0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
> + {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
> + {0x0005, RX_DIAG_REE_DAC_CTRL}
> +};
> +
> +static struct cdns_torrent_vals ml_pcie_100_no_ssc_cmn_vals = {
> + .reg_pairs = ml_pcie_100_no_ssc_cmn_regs,
> + .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_cmn_regs),
> +};
> +
> +static struct cdns_torrent_vals ml_pcie_100_no_ssc_rx_ln_vals = {
> + .reg_pairs = ml_pcie_100_no_ssc_rx_ln_regs,
> + .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_rx_ln_regs),
> +};
> +
> +/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
> +static struct cdns_reg_pairs ml_pcie_100_int_ssc_cmn_regs[] = {
> + {0x0004, CMN_PLL0_DSM_DIAG_M0},
> + {0x0004, CMN_PLL1_DSM_DIAG_M0},
> + {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
> + {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
> + {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
> + {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
> + {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
> + {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
> + {0x0064, CMN_PLL0_INTDIV_M0},
> + {0x0050, CMN_PLL1_INTDIV_M0},
> + {0x0002, CMN_PLL0_FRACDIVH_M0},
> + {0x0002, CMN_PLL1_FRACDIVH_M0},
> + {0x0044, CMN_PLL0_HIGH_THR_M0},
> + {0x0036, CMN_PLL1_HIGH_THR_M0},
> + {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
> + {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
> + {0x0001, CMN_PLL0_SS_CTRL1_M0},
> + {0x0001, CMN_PLL1_SS_CTRL1_M0},
> + {0x011B, CMN_PLL0_SS_CTRL2_M0},
> + {0x011B, CMN_PLL1_SS_CTRL2_M0},
> + {0x006E, CMN_PLL0_SS_CTRL3_M0},
> + {0x0058, CMN_PLL1_SS_CTRL3_M0},
> + {0x000E, CMN_PLL0_SS_CTRL4_M0},
> + {0x0012, CMN_PLL1_SS_CTRL4_M0},
> + {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
> + {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
> + {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
> + {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
> + {0x0003, CMN_PLL0_VCOCAL_TCTRL},
> + {0x0003, CMN_PLL1_VCOCAL_TCTRL},
> + {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
> + {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
> + {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
> + {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
> + {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
> + {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
> +};
> +
> +static struct cdns_torrent_vals ml_pcie_100_int_ssc_cmn_vals = {
> + .reg_pairs = ml_pcie_100_int_ssc_cmn_regs,
> + .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_cmn_regs),
> +};
> +
> /* SGMII and QSGMII link configuration */
> static struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = {
> {0x0002, PHY_PLL_CFG}
> @@ -4475,7 +4573,7 @@ static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
> .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
> };
>
> -/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
> +/* For PCIe (with some other protocol), 100 MHz Ref clk, internal SSC */
> static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
> {0x0004, CMN_PLL0_DSM_DIAG_M0},
> {0x0004, CMN_PLL0_DSM_DIAG_M1},
> @@ -4614,6 +4712,7 @@ static struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
>
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
> + {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_link_cmn_vals},
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
> @@ -4650,6 +4749,7 @@ static struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
>
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
> + {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_xcvr_diag_ln_vals},
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
> {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
> @@ -4700,6 +4800,10 @@ static struct cdns_torrent_vals_entry cmn_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
> @@ -4782,6 +4886,10 @@ static struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
> @@ -4864,6 +4972,10 @@ static struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> @@ -4982,6 +5094,10 @@ static struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
> @@ -5098,6 +5214,10 @@ static struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
> @@ -5180,6 +5300,10 @@ static struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
> @@ -5262,6 +5386,10 @@ static struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
>
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> + {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> +
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
> --
> 2.40.1
>
>
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