linux-kernel - Re: [PATCH v2 2/3] riscv: dts: add mailbox for Sophgo cv18x SoCs

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Message-ID: <3a7996d6-1137-44b8-b35d-d9c56bd98277@sifive.com>
Date: Thu, 18 Jul 2024 20:19:01 -0500
From: Samuel Holland <samuel.holland@...ive.com>
To: Yuntao Dai <d1581209858@...e.com>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
 linux-riscv@...ts.infradead.org, jassisinghbrar@...il.com, robh@...nel.org,
 krzk+dt@...nel.org, conor+dt@...nel.org, unicorn_wang@...look.com,
 inochiama@...look.com, paul.walmsley@...ive.com, palmer@...belt.com,
 aou@...s.berkeley.edu
Subject: Re: [PATCH v2 2/3] riscv: dts: add mailbox for Sophgo cv18x SoCs

On 2024-07-14 11:36 AM, Yuntao Dai wrote:
> Add mailbox node for Sophgo cv18x SoCs
> 
> Signed-off-by: Yuntao Dai <d1581209858@...e.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 891932ae4..1c7035737 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -310,5 +310,14 @@
>  			reg = <0x74000000 0x10000>;
>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>  		};
> +
> +		mailbox: mailbox@...0000 {

Please keep nodes sorted by unit address.

> +			compatible = "sophgo,cv1800-mailbox";
> +			reg = <0x01900000 0x1000>;
> +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mailbox";
> +			interrupt-parent = <&plic>;
> +			#mbox-cells = <2>;
> +		};
>  	};
>  };