linux-kernel - Re: [PATCH] MIPS: SMP-CPS: Fix address for GCR

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Message-Id: <302ca8fb-0185-4872-9d82-d472854e5a43@app.fastmail.com>
Date: Sat, 20 Jul 2024 11:13:12 +0800
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Gregory CLEMENT" <gregory.clement@...tlin.com>,
 "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>,
 "paulburton@...nel.org" <paulburton@...nel.org>
Cc: "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 linux-kernel@...r.kernel.org,
 Théo Lebrun <theo.lebrun@...tlin.com>,
 "Vladimir Kondratiev" <vladimir.kondratiev@...ileye.com>,
 "Tawfik Bayouk" <tawfik.bayouk@...ileye.com>,
 "Thomas Petazzoni" <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for I6500



在2024年7月19日七月 下午10:14，Gregory CLEMENT写道：
> Unlike most other MIPS CPUs, the I6500 CPUs have different address
> offsets for the Global CSR Access Privilege register. In the "MIPS64
> I6500 Multiprocessing System Programmer's Guide," it is stated that
> "the Global CSR Access Privilege register is located at offset 0x0120"
> in section 5.4.
>
> However, this is not the case for other MIPS64 CPUs such as the
> P6600. In the "MIPS64® P6600 Multiprocessing System Software User's
> Guide," section 6.4.2.6 states that the GCR_ACCESS register has an
> offset of 0x0020.

Hi Gregory,

I confirmed this is a CM3 feature rather than CPU core (Samruai) feature.

Please use CM version to select register region.
(And perhaps Cc stable for this patch?)

Thanks
- Jiaxun

>
> This fix allows to use the VP cores in SMP mode.
>
> Based on the work of Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
>
> Fixes: 859aeb1b0dd1 ("MIPS: Probe the I6500 CPU")
> Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
> ---
>  arch/mips/include/asm/mips-cm.h | 4 ++++
>  arch/mips/kernel/smp-cps.c      | 5 ++++-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
> index 3d9efc802e36..41bf9b3a98fb 100644
> --- a/arch/mips/include/asm/mips-cm.h
> +++ b/arch/mips/include/asm/mips-cm.h
> @@ -240,6 +240,10 @@ GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
>  GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
>  #define CM_GCR_CPC_STATUS_EX			BIT(0)
> 
> +/* GCR_ACCESS - Controls core/IOCU access to GCRs */
> +GCR_ACCESSOR_RW(32, 0x120, access_i6500)
> +#define CM_GCR_ACCESS_ACCESSEN			GENMASK(7, 0)
> +
>  /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 
> */
>  GCR_ACCESSOR_RW(32, 0x130, l2_config)
>  #define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index e074138ffd7f..60590890b6da 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -325,7 +325,10 @@ static void boot_core(unsigned int core, unsigned 
> int vpe_id)
>  	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
> 
>  	/* Ensure the core can access the GCRs */
> -	set_gcr_access(1 << core);
> +	if (current_cpu_type() != CPU_I6500)
> +		set_gcr_access(1 << core);
> +	else
> +		set_gcr_access_i6500(1 << core);
> 
>  	if (mips_cpc_present()) {
>  		/* Reset the core */
>
> ---
> base-commit: 9298d51eb3af24f88b211087eb698399f9efa439
> change-id: 20240719-smp_i6500-8cb233878c41
>
> Best regards,
> -- 
> Gregory CLEMENT <gregory.clement@...tlin.com>

-- 
- Jiaxun