linux-kernel - Re: [PATCH] MIPS: SMP-CPS: Fix address for GCR

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Message-Id: <1811a5de-1a7f-46a9-b8ad-a76ec51f3a23@app.fastmail.com>
Date: Mon, 22 Jul 2024 18:36:37 +0800
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Gregory CLEMENT" <gregory.clement@...tlin.com>,
 "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>,
 "paulburton@...nel.org" <paulburton@...nel.org>
Cc: "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 linux-kernel@...r.kernel.org,
 Théo Lebrun <theo.lebrun@...tlin.com>,
 "Vladimir Kondratiev" <vladimir.kondratiev@...ileye.com>,
 "Tawfik Bayouk" <tawfik.bayouk@...ileye.com>,
 "Thomas Petazzoni" <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for I6500



在2024年7月22日七月 下午6:17，Gregory CLEMENT写道：
> Gregory CLEMENT <gregory.clement@...tlin.com> writes:
>
>> Hello Jiaxun,
>>
>>> 在2024年7月20日七月 上午11:13，Jiaxun Yang写道：
>>>> 在2024年7月19日七月 下午10:14，Gregory CLEMENT写道：
>>>>> Unlike most other MIPS CPUs, the I6500 CPUs have different address
>>>>> offsets for the Global CSR Access Privilege register. In the "MIPS64
>>>>> I6500 Multiprocessing System Programmer's Guide," it is stated that
>>>>> "the Global CSR Access Privilege register is located at offset 0x0120"
>>>>> in section 5.4.
>>>>>
>>>>> However, this is not the case for other MIPS64 CPUs such as the
>>>>> P6600. In the "MIPS64® P6600 Multiprocessing System Software User's
>>>>> Guide," section 6.4.2.6 states that the GCR_ACCESS register has an
>>>>> offset of 0x0020.
>>>>
>>>> Hi Gregory,
>>>>
>>>> I confirmed this is a CM3 feature rather than CPU core (Samruai) feature.
>>>
>>> Oh I’m not really sure if it’s CM 3.5 only.
>>>
>>> Let me check this Monday once I can checkout old design database for
>>> I6400.
>>
>> Ok, so I am waiting for your feedback :)
>> And I am also trying to see if I can find the datasheet for I6400.
>>>
>>> Hardware resets GCR_ACCESS to the most permissive value so I assume
>>> it’s your bootloader doing wired hacks.
>
> I found an I6400 datasheet [1] and in the "5.4 CM Register Access
> Permissions" paragraph, it is written "the Global CSR Access Privilege
> register located at offset 0x0120". So it has the same offset as the
> I6500.

Yes, I hand confirmed this modification was made to CM block at transition
from CM2.5 to CM3.

Other unannounced CM3 products (Daiymo, King for people knowing codenames)
have this change as well.

So for this modification, you can safely do:
mips_cm_revision() >= CM_REV_CM3

And perhaps name this GCR after access_cm3.

Thanks
- Jiaxun

>
> Gregory
>
> [1]: 
> https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MIPS_Warrior_I6400_ProgrammerGuide_MD01196_P_1.00.pdf
>
>>
>> Indeed, other bootloaders seem to not modify it, so that's why I think
>> the issue was never detected until now. However, we want to be as
>> independent as possible from the bootloader, so we really need to fix
>> it.
>>
>> Thanks for your review!
>>
>> Gregory
>>

-- 
- Jiaxun