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Message-ID: <20240722142502.224694-1-sandipan.das@amd.com>
Date: Mon, 22 Jul 2024 19:55:02 +0530
From: Sandipan Das <sandipan.das@....com>
To: <linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: <x86@...nel.org>, <peterz@...radead.org>, <mingo@...hat.com>,
<acme@...nel.org>, <namhyung@...nel.org>, <mark.rutland@....com>,
<alexander.shishkin@...ux.intel.com>, <jolsa@...nel.org>,
<irogers@...gle.com>, <adrian.hunter@...el.com>, <kan.liang@...ux.intel.com>,
<tglx@...utronix.de>, <bp@...en8.de>, <dave.hansen@...ux.intel.com>,
<hpa@...or.com>, <gleb@...hat.com>, <mizhang@...gle.com>,
<ravi.bangoria@....com>, <ananth.narayan@....com>, <sandipan.das@....com>
Subject: [PATCH] perf/x86: Do not set bit width for unavailable counters
Not all x86 processors have fixed counters. It may also be the case that
a processor has only fixed counters and no general-purpose counters. Set
the bit widths corresponding to each counter type only if such counters
are available.
Fixes: b3d9468a8bd2 ("perf, x86: Expose perf capability to other modules")
Signed-off-by: Sandipan Das <sandipan.das@....com>
---
arch/x86/events/core.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 975b0f8a0b00..8405f6859d79 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2983,8 +2983,13 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
cap->version = x86_pmu.version;
cap->num_counters_gp = x86_pmu_num_counters(NULL);
cap->num_counters_fixed = x86_pmu_num_counters_fixed(NULL);
- cap->bit_width_gp = x86_pmu.cntval_bits;
- cap->bit_width_fixed = x86_pmu.cntval_bits;
+
+ if (cap->num_counters_gp)
+ cap->bit_width_gp = x86_pmu.cntval_bits;
+
+ if (cap->num_counters_fixed)
+ cap->bit_width_fixed = x86_pmu.cntval_bits;
+
cap->events_mask = (unsigned int)x86_pmu.events_maskl;
cap->events_mask_len = x86_pmu.events_mask_len;
cap->pebs_ept = x86_pmu.pebs_ept;
--
2.43.0
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