linux-kernel - [RFC v7 2/6] dt-bindings: interrupt-controller: document PolarFire SoC's gpio interrupt mux

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20240723-uncouple-enforcer-7c48e4a4fefe@wendy>
Date: Tue, 23 Jul 2024 12:27:11 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: <linux-kernel@...r.kernel.org>
CC: <conor@...nel.org>, <conor.dooley@...rochip.com>, Marc Zyngier
	<maz@...nel.org>, Daire McNamara <daire.mcnamara@...rochip.com>, "Linus
 Walleij" <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>,
	"Rob Herring" <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	"Thomas Gleixner" <tglx@...utronix.de>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
	<linux-riscv@...ts.infradead.org>, <linux-gpio@...r.kernel.org>,
	<devicetree@...r.kernel.org>
Subject: [RFC v7 2/6] dt-bindings: interrupt-controller: document PolarFire SoC's gpio interrupt mux

On PolarFire SoC there are more GPIO interrupts than there are interrupt
lines available on the PLIC, and a runtime configurable mux is used to
decide which interrupts are assigned direct connections to the PLIC &
which are relegated to sharing a line.
This mux is, in our reference configuration, written by platform
firmware during boot based on the FPGA's configuration.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 .../microchip,mpfs-gpio-irq-mux.yaml          | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,mpfs-gpio-irq-mux.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,mpfs-gpio-irq-mux.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,mpfs-gpio-irq-mux.yaml
new file mode 100644
index 0000000000000..89ed3a630eef3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,mpfs-gpio-irq-mux.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/microchip,mpfs-gpio-irq-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Polarfire SoC GPIO Interrupt Mux
+
+maintainers:
+  - Conor Dooley <conor.dooley@...rochip.com>
+
+description: |
+  There are 3 GPIO controllers on this SoC, of which:
+  - GPIO controller 0 has 14 GPIOs
+  - GPIO controller 1 has 24 GPIOs
+  - GPIO controller 2 has 32 GPIOs
+
+  All GPIOs are capable of generating interrupts, for a total of 70.
+  There are only 41 IRQs available however, so a configurable mux is used to
+  ensure all GPIOs can be used for interrupt generation.
+  38 of the 41 interrupts are in what the documentation calls "direct mode",
+  as they provide an exclusive connection from a GPIO to the PLIC.
+  The 3 remaining interrupts are used to mux the interrupts which do not have
+  a exclusive connection, one for each GPIO controller.
+
+properties:
+  compatible:
+    const: microchip,mpfs-gpio-irq-mux
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupts:
+    description:
+      The first 38 entries must be the "direct" interrupts, for exclusive
+      connections to the PLIC. The final 3 entries must be the
+      "non-direct"/muxed connections for each of GPIO controller 0, 1 & 2
+      respectively.
+    maxItems: 41
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#interrupt-cells"
+  - interrupt-controller
+
+additionalProperties: false
+
+examples:
+  - |
+    irqmux: interrupt-controller@...02054 {
+        compatible = "microchip,mpfs-gpio-irq-mux";
+        reg = <0x20002054 0x4>;
+        interrupt-parent = <&plic>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        status = "okay";
+        interrupts = <13>, <14>, <15>, <16>,
+                     <17>, <18>, <19>, <20>,
+                     <21>, <22>, <23>, <24>,
+                     <25>, <26>, <27>, <28>,
+                     <29>, <30>, <31>, <32>,
+                     <33>, <34>, <35>, <36>,
+                     <37>, <38>, <39>, <40>,
+                     <41>, <42>, <43>, <44>,
+                     <45>, <46>, <47>, <48>,
+                     <49>, <50>, <51>, <52>,
+                     <53>;
+    };
+...
-- 
2.43.2