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Message-ID: <20240723-framing-chaos-9f8e2df8889d@wendy>
Date: Tue, 23 Jul 2024 12:27:15 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: <linux-kernel@...r.kernel.org>
CC: <conor@...nel.org>, <conor.dooley@...rochip.com>, Marc Zyngier
<maz@...nel.org>, Daire McNamara <daire.mcnamara@...rochip.com>, "Linus
Walleij" <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>,
"Rob Herring" <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
"Thomas Gleixner" <tglx@...utronix.de>, Paul Walmsley
<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
<linux-riscv@...ts.infradead.org>, <linux-gpio@...r.kernel.org>,
<devicetree@...r.kernel.org>
Subject: [RFC v7 6/6] riscv: dts: microchip: update gpio interrupts to better match the SoC
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used to
ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct mode",
as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not have
a exclusive connection, one for each GPIO controller.
Setting of the mux should be done by the platform's firmware at boot, based
on the output of the "MSS Configurator" (FPGA configuration tool).
The microchip,mpfs-gpio binding suffered greatly due to being written
with a narrow minded view of the controller, and the interrupt bits
ended up incorrect. It was mistakenly assumed that the interrupt
configuration was set by platform firmware, based on the FPGA
configuration, and that the GPIO DT nodes were the only way to really
communicate interrupt configuration to software.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
.../boot/dts/microchip/mpfs-icicle-kit.dts | 8 ---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 50 +++++++++++++++++--
2 files changed, 45 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index f80df225f72b4..7a9822d2a8819 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -83,14 +83,6 @@ &core_pwm0 {
};
&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 9883ca3554c50..e31e0aacb943b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -465,39 +465,79 @@ mac1: ethernet@...12000 {
status = "disabled";
};
- gpio0: gpio@...20000 {
- compatible = "microchip,mpfs-gpio";
- reg = <0x0 0x20120000 0x0 0x1000>;
+ irqmux: interrupt-controller@...02054 {
+ compatible = "microchip,mpfs-gpio-irq-mux";
+ reg = <0x0 0x20002054 0x0 0x4>;
interrupt-parent = <&plic>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <13>, <14>, <15>, <16>,
+ <17>, <18>, <19>, <20>,
+ <21>, <22>, <23>, <24>,
+ <25>, <26>, <27>, <28>,
+ <29>, <30>, <31>, <32>,
+ <33>, <34>, <35>, <36>,
+ <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>,
+ <45>, <46>, <47>, <48>,
+ <49>, <50>, <51>, <52>,
+ <53>;
+ };
+
+ gpio0: gpio@...20000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&irqmux>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>,
+ <12>, <13>;
clocks = <&clkcfg CLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
+ ngpios = <14>;
status = "disabled";
};
gpio1: gpio@...21000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20121000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <32>, <33>, <34>, <35>,
+ <36>, <37>, <38>, <39>,
+ <40>, <41>, <42>, <43>,
+ <44>, <45>, <46>, <47>,
+ <48>, <49>, <50>, <51>,
+ <52>, <53>, <54>, <55>;
clocks = <&clkcfg CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
+ ngpios = <24>;
status = "disabled";
};
gpio2: gpio@...22000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <64>, <65>, <66>, <67>,
+ <68>, <69>, <70>, <71>,
+ <72>, <73>, <74>, <75>,
+ <76>, <77>, <78>, <79>,
+ <80>, <81>, <82>, <83>,
+ <84>, <85>, <86>, <87>,
+ <88>, <89>, <90>, <91>,
+ <92>, <93>, <94>, <95>;
clocks = <&clkcfg CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
+ ngpios = <32>;
status = "disabled";
};
--
2.43.2
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