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Message-ID: <20240723173538.3493935-6-Shyam-sundar.S-k@amd.com>
Date: Tue, 23 Jul 2024 23:05:38 +0530
From: Shyam Sundar S K <Shyam-sundar.S-k@....com>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>, Jarkko Nikula
<jarkko.nikula@...ux.intel.com>
CC: Guruvendra Punugupati <Guruvendra.Punugupati@....com>, Krishnamoorthi M
<krishnamoorthi.m@....com>, <linux-i3c@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, Shyam Sundar S K <Shyam-sundar.S-k@....com>
Subject: [PATCH 5/5] i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold
The current driver sets the response buffer threshold value to 1
(N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
I3C controller only generates interrupts when the response buffer
threshold value is set to 0 (1 DWORD).
Therefore, a quirk is added to set the response buffer threshold value
to 0.
Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@....com>
Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@....com>
Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@....com>
Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@....com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@....com>
---
drivers/i3c/master/mipi-i3c-hci/core.c | 4 ++++
drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++
drivers/i3c/master/mipi-i3c-hci/hci_quirks.c | 12 ++++++++++++
3 files changed, 18 insertions(+)
diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c
index 9fc142ca7532..2da00a5b590b 100644
--- a/drivers/i3c/master/mipi-i3c-hci/core.c
+++ b/drivers/i3c/master/mipi-i3c-hci/core.c
@@ -148,6 +148,10 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m)
if (ret)
return ret;
+ /* Set RESP_BUF_THLD to 0(n) to get 1(n+1) response */
+ if (hci->quirks & HCI_QUIRK_AMD_RESP_BUF_THLD)
+ amd_set_resp_buf_thld(hci);
+
reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL));
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mipi-i3c-hci/hci.h
index f4ec6dcb2ecf..07b90a68ec5e 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci.h
+++ b/drivers/i3c/master/mipi-i3c-hci/hci.h
@@ -141,6 +141,7 @@ struct i3c_hci_dev_data {
#define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */
#define HCI_QUIRK_AMD_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */
#define HCI_QUIRK_AMD_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */
+#define HCI_QUIRK_AMD_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */
/* global functions */
@@ -150,5 +151,6 @@ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
void amd_i3c_hci_quirks_init(struct i3c_hci *hci);
void amd_set_od_pp_timing(struct i3c_hci *hci);
+void amd_set_resp_buf_thld(struct i3c_hci *hci);
#endif
diff --git a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
index 9d8c5eedc8cc..503c81c504f1 100644
--- a/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
+++ b/drivers/i3c/master/mipi-i3c-hci/hci_quirks.c
@@ -20,11 +20,14 @@
#define AMD_SCL_I3C_OD_TIMING 0x00cf00cf
#define AMD_SCL_I3C_PP_TIMING 0x00160016
+#define QUEUE_THLD_CTRL 0xD0
+
void amd_i3c_hci_quirks_init(struct i3c_hci *hci)
{
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
hci->quirks |= HCI_QUIRK_AMD_PIO_MODE;
hci->quirks |= HCI_QUIRK_AMD_OD_PP_TIMING;
+ hci->quirks |= HCI_QUIRK_AMD_RESP_BUF_THLD;
}
}
@@ -39,3 +42,12 @@ void amd_set_od_pp_timing(struct i3c_hci *hci)
data |= W0_MASK(18, 16);
reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);
}
+
+void amd_set_resp_buf_thld(struct i3c_hci *hci)
+{
+ u32 data;
+
+ data = reg_read(QUEUE_THLD_CTRL);
+ data = data & ~W0_MASK(15, 8);
+ reg_write(QUEUE_THLD_CTRL, data);
+}
--
2.25.1
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