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Message-ID: <18f5565f-11f5-49ce-a816-366cff25b703@kernel.org>
Date: Wed, 24 Jul 2024 12:12:03 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Sunyeal Hong <sunyeal.hong@...sung.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU
bindings
On 23/07/2024 00:33, Sunyeal Hong wrote:
> Add dt-schema for ExynosAuto v920 SoC clock controller.
> Add device tree clock binding definitions for below CMU blocks.
>
> - CMU_TOP
> - CMU_PERIC0
>
> Signed-off-by: Sunyeal Hong <sunyeal.hong@...sung.com>
> ---
> .../clock/samsung,exynosautov920-clock.yaml | 115 +++++++++++
> .../clock/samsung,exynosautov920.h | 191 ++++++++++++++++++
> 2 files changed, 306 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
> create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
> new file mode 100644
> index 000000000000..90f9f17da959
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung ExynosAuto v920 SoC clock controller
> +
> +maintainers:
> + - Sunyeal Hong <sunyeal.hong@...sung.com>
> + - Chanwoo Choi <cw00.choi@...sung.com>
> + - Krzysztof Kozlowski <krzk@...nel.org>
> + - Sylwester Nawrocki <s.nawrocki@...sung.com>
> +
> +description: |
> + ExynosAuto v920 clock controller is comprised of several CMU units, generating
> + clocks for different domains. Those CMU units are modeled as separate device
> + tree nodes, and might depend on each other. Root clocks in that clock tree are
> + two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
> + The external OSCCLK must be defined as fixed-rate clock in dts.
> +
> + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> + dividers; all other clocks of function blocks (other CMUs) are usually
> + derived from CMU_TOP.
> +
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All clocks available for usage
> + in clock consumer nodes are defined as preprocessor macros in
> + 'include/dt-bindings/clock/samsung,exynosautov920.h' header.
> +
> +properties:
> + compatible:
> + enum:
> + - samsung,exynosautov920-cmu-top
> + - samsung,exynosautov920-cmu-peric0
> +
> + clocks:
> + minItems: 1
> + maxItems: 3
> +
> + clock-names:
> + minItems: 1
> + maxItems: 3
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynosautov920-cmu-top
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (38.4 MHz)
> +
> + clock-names:
> + items:
> + - const: oscclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynosautov920-cmu-peric0
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (38.4 MHz)
> + - description: CMU_PERIC0 NOC clock (from CMU_TOP)
> + - description: CMU_PERIC0 IP clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: noc
> + - const: ip
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node for CMU_PERIC0
> + - |
> + #include <dt-bindings/clock/samsung,exynosautov920.h>
> +
> + cmu_peric0: clock-controller@...00000 {
> + compatible = "samsung,exynosautov920-cmu-peric0";
> + reg = <0x10800000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&xtcxo>,
> + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
> + <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
> + clock-names = "oscclk",
> + "noc",
> + "ip";
> + };
> +
> +...
> diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
> new file mode 100644
> index 000000000000..ad89728a4396
> --- /dev/null
> +++ b/include/dt-bindings/clock/samsung,exynosautov920.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2024 Samsung Electronics Co., Ltd.
> + * Author: Sunyeal Hong <sunyeal.hong@...sung.com>
> + *
> + * Device Tree binding constants for ExynosAuto v920 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
> +#define _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H
> +
> +/* CMU_TOP */
> +#define FOUT_SHARED0_PLL 1
> +#define FOUT_SHARED1_PLL 2
> +#define FOUT_SHARED2_PLL 3
> +#define FOUT_SHARED3_PLL 4
> +#define FOUT_SHARED4_PLL 5
> +#define FOUT_SHARED5_PLL 6
> +#define FOUT_MMC_PLL 7
> +
> +/* MUX in CMU_TOP */
> +#define MOUT_SHARED0_PLL 101
This is some odd numbering. Numbers start from 0 or 1 and are continuous.
Best regards,
Krzysztof
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