linux-kernel - [PATCH 06/17] dt-bindings: riscv: sifive-l2: add a PIC64GX compatible

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Message-ID: <20240725121609.13101-7-pierre-henry.moussay@microchip.com>
Date: Thu, 25 Jul 2024 13:15:58 +0100
From: <pierre-henry.moussay@...rochip.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
	Samuel Holland <samuel.holland@...ive.com>, Palmer Dabbelt
	<palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>
CC: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>,
	<devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
Subject: [PATCH 06/17] dt-bindings: riscv: sifive-l2: add a PIC64GX compatible

From: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>

The PIC64GX use an IP similar to MPFS one, therefore add compatibility with
MPFS as fallback

Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>
---
 Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..9d064feb2ab1 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -47,6 +47,11 @@ properties:
           - const: microchip,mpfs-ccache
           - const: sifive,fu540-c000-ccache
           - const: cache
+      - items:
+          - const: microchip,pic64gx-ccache
+          - const: microchip,mpfs-ccache
+          - const: sifive,fu540-c000-ccache
+          - const: cache
 
   cache-block-size:
     const: 64
@@ -93,6 +98,7 @@ allOf:
               - starfive,jh7100-ccache
               - starfive,jh7110-ccache
               - microchip,mpfs-ccache
+              - microchip,pic64gx-ccache
 
     then:
       properties:
-- 
2.30.2