linux-kernel - [PATCH 5/5] arm64: dts: renesas: r9a07g044c1: Correct GICD and GICR sizes

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Message-Id: <20240725133932.739936-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Thu, 25 Jul 2024 14:39:32 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
	Marc Zyngier <maz@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Prabhakar <prabhakar.csengg@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 5/5] arm64: dts: renesas: r9a07g044c1: Correct GICD and GICR sizes

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

The RZ/G2LC SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
and the GICR is 128kB per CPU.

Fixes: 3a3c2a48d8c6b ("arm64: dts: renesas: Add initial DTSI for RZ/G2LC SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
index 56a979e82c4f..18f092c4090c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi
@@ -17,6 +17,11 @@ cpus {
 	};
 };
 
+&gic {
+	reg = <0x0 0x11900000 0 0x20000>,
+	      <0x0 0x11940000 0 0x20000>;
+};
+
 &soc {
 	/delete-node/ ssi@...4a800;
 	/delete-node/ serial@...4c800;
-- 
2.34.1