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Message-ID: <20240725-trance-creme-d71484a00581@spud>
Date: Thu, 25 Jul 2024 15:19:43 +0100
From: Conor Dooley <conor@...nel.org>
To: pierre-henry.moussay@...rochip.com
Cc: Conor Dooley <conor.dooley@...rochip.com>,
Daire McNamara <daire.mcnamara@...rochip.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX
compatibility
On Thu, Jul 25, 2024 at 01:15:59PM +0100, pierre-henry.moussay@...rochip.com wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>
>
> PIC64GX SoC has clock compatibles with the MPFS IP
These commit messages don't really make sense. It should read something
like "The pic64gx SoC has has Clock Conditioning Circuitry compatible
with that on PolarFire SoC" or something along those lines.
>
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@...rochip.com>
> ---
> .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> index f1770360798f..9a6b50527c42 100644
> --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> @@ -17,7 +17,11 @@ description: |
>
> properties:
> compatible:
> - const: microchip,mpfs-ccc
> + oneOf:
> + - items:
> + - const: microchip,pic64gx-ccc
> + - const: microchip,mpfs-ccc
> + - const: microchip,mpfs-ccc
>
> reg:
> items:
> --
> 2.30.2
>
>
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> linux-riscv@...ts.infradead.org
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