linux-kernel - Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and GICR sizes

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Message-ID: <CA+V-a8uYKTpXjsW=p+jHpCtnsNjaAEA8xHNr=KeH=4g5jXmr5A@mail.gmail.com>
Date: Thu, 25 Jul 2024 16:10:56 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Marc Zyngier <maz@...nel.org>, Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 4/5] arm64: dts: renesas: r9a07g044(l1): Correct GICD and
 GICR sizes

Hi Geert,

On Thu, Jul 25, 2024 at 4:07 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Jul 25, 2024 at 4:59 PM Lad, Prabhakar
> <prabhakar.csengg@...il.com> wrote:
> > On Thu, Jul 25, 2024 at 3:53 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > > On Thu, Jul 25, 2024 at 3:41 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > >
> > > > The RZ/G2L SoC is equipped with the GIC-600. The GICD + GICDA is 128kB,
> > > > and the GICR is 128kB per CPU.
> > > >
> > > > Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > > @@ -1043,8 +1043,8 @@ gic: interrupt-controller@...00000 {
> > > >                         #interrupt-cells = <3>;
> > > >                         #address-cells = <0>;
> > > >                         interrupt-controller;
> > > > -                       reg = <0x0 0x11900000 0 0x40000>,
> > > > -                             <0x0 0x11940000 0 0x60000>;
> > > > +                       reg = <0x0 0x11900000 0 0x20000>,
> > > > +                             <0x0 0x11940000 0 0x40000>;
> > > >                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > > >                 };
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > > index 9cf27ca9f1d2..6f4d4dc13f50 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> > > > @@ -16,3 +16,8 @@ cpus {
> > > >                 /delete-node/ cpu@100;
> > > >         };
> > > >  };
> > > > +
> > > > +&gic {
> > > > +       reg = <0x0 0x11900000 0 0x20000>,
> > > > +             <0x0 0x11940000 0 0x20000>;
> > > > +};
> > >
> > > What's the point of overriding this here?
> > >
> > Are you suggesting we drop this, as we have no users for it currently?
>
> I didn't mean to drop it because we have no users of r9a07g044l1.dtsi.
> I am just wondering what would be the side-effect of not overriding it?
Not sure what side-effects we would see, maybe the IRQ maintainers can
comment on it.

> After all, all r9a07g044 SoC variants have the same GIC hardware block?
>
I would assume so, I dont have a r9a07g044l1 SoC to verify it. Maybe I
will drop this until it's verified.

Cheers,
Prabhakar