linux-kernel - Re: [PATCH v8 00/13] riscv: Add support for xtheadvector

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Message-Id: 
 <172193703481.21409.18294756229042401950.git-patchwork-notify@kernel.org>
Date: Thu, 25 Jul 2024 19:50:34 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Charlie Jenkins <charlie@...osinc.com>
Cc: linux-riscv@...ts.infradead.org, conor@...nel.org, robh@...nel.org,
 krzk+dt@...nel.org, paul.walmsley@...ive.com, palmer@...belt.com,
 aou@...s.berkeley.edu, jszhang@...nel.org, wens@...e.org,
 jernej.skrabec@...il.com, samuel@...lland.org, samuel.holland@...ive.com,
 corbet@....net, shuah@...nel.org, guoren@...nel.org, evan@...osinc.com,
 andy.chiu@...ive.com, jrtc27@...c27.com, ajones@...tanamicro.com,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-sunxi@...ts.linux.dev, linux-doc@...r.kernel.org,
 linux-kselftest@...r.kernel.org, conor.dooley@...rochip.com, heiko@...ech.de
Subject: Re: [PATCH v8 00/13] riscv: Add support for xtheadvector

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:

On Wed, 24 Jul 2024 21:16:17 -0700 you wrote:
> xtheadvector is a custom extension that is based upon riscv vector
> version 0.7.1 [1]. All of the vector routines have been modified to
> support this alternative vector version based upon whether xtheadvector
> was determined to be supported at boot.
> 
> vlenb is not supported on the existing xtheadvector hardware, so a
> devicetree property thead,vlenb is added to provide the vlenb to Linux.
> 
> [...]

Here is the summary with links:
  - [v8,01/13] dt-bindings: riscv: Add xtheadvector ISA extension description
    https://git.kernel.org/riscv/c/8a0fe092f06f
  - [v8,02/13] dt-bindings: cpus: add a thead vlen register length property
    https://git.kernel.org/riscv/c/7c527250e3fc
  - [v8,03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
    https://git.kernel.org/riscv/c/7d174ad15cc5
  - [v8,04/13] riscv: Add thead and xtheadvector as a vendor extension
    https://git.kernel.org/riscv/c/db44682eb864
  - [v8,05/13] riscv: vector: Use vlenb from DT for thead
    https://git.kernel.org/riscv/c/513baedd87c2
  - [v8,06/13] RISC-V: define the elements of the VCSR vector CSR
    https://git.kernel.org/riscv/c/8d141ea2e107
  - [v8,07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT
    https://git.kernel.org/riscv/c/91c52b2d902e
  - [v8,08/13] riscv: Add xtheadvector instruction definitions
    https://git.kernel.org/riscv/c/a3f2adbddf80
  - [v8,09/13] riscv: vector: Support xtheadvector save/restore
    https://git.kernel.org/riscv/c/efc8d713bc11
  - [v8,10/13] riscv: hwprobe: Add thead vendor extension probing
    https://git.kernel.org/riscv/c/75a4b53cbc9d
  - [v8,11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension
    https://git.kernel.org/riscv/c/8302596e9d0c
  - [v8,12/13] selftests: riscv: Fix vector tests
    https://git.kernel.org/riscv/c/a1d098335922
  - [v8,13/13] selftests: riscv: Support xtheadvector in vector tests
    https://git.kernel.org/riscv/c/d81701d2ba9b

You are awesome, thank you!
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