linux-kernel - Re: [PATCH v3 6/7] Drivers: hv: vmbus: Get the IRQ number from DT

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Message-Id: <ce8c1e88-2d2f-44de-bd43-c05e274c2660@app.fastmail.com>
Date: Sat, 27 Jul 2024 11:17:20 +0200
From: "Arnd Bergmann" <arnd@...db.de>
To: "Krzysztof Kozlowski" <krzk@...nel.org>,
 "Roman Kisel" <romank@...ux.microsoft.com>, bhelgaas@...gle.com,
 "Borislav Petkov" <bp@...en8.de>,
 "Catalin Marinas" <catalin.marinas@....com>,
 "Dave Hansen" <dave.hansen@...ux.intel.com>,
 "Dexuan Cui" <decui@...rosoft.com>, "Haiyang Zhang" <haiyangz@...rosoft.com>,
 "H. Peter Anvin" <hpa@...or.com>,
 Krzysztof Wilczyński <kw@...ux.com>,
 "K. Y. Srinivasan" <kys@...rosoft.com>, "Len Brown" <lenb@...nel.org>,
 "Lorenzo Pieralisi" <lpieralisi@...nel.org>,
 "Ingo Molnar" <mingo@...hat.com>, "Rafael J . Wysocki" <rafael@...nel.org>,
 "Rob Herring" <robh@...nel.org>, "Thomas Gleixner" <tglx@...utronix.de>,
 "Wei Liu" <wei.liu@...nel.org>, "Will Deacon" <will@...nel.org>,
 linux-acpi@...r.kernel.org, Linux-Arch <linux-arch@...r.kernel.org>,
 linux-arm-kernel@...ts.infradead.org, linux-hyperv@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org, x86@...nel.org
Cc: apais@...rosoft.com, benhill@...rosoft.com, ssengar@...rosoft.com,
 sunilmut@...rosoft.com, vdso@...bites.dev
Subject: Re: [PATCH v3 6/7] Drivers: hv: vmbus: Get the IRQ number from DT

On Sat, Jul 27, 2024, at 10:56, Krzysztof Kozlowski wrote:
> On 27/07/2024 00:59, Roman Kisel wrote:
>> @@ -2338,6 +2372,21 @@ static int vmbus_device_add(struct platform_device *pdev)
>>  		cur_res = &res->sibling;
>>  	}
>>  
>> +	/*
>> +	 * Hyper-V always assumes DMA cache coherency, and the DMA subsystem
>> +	 * might default to 'not coherent' on some architectures.
>> +	 * Avoid high-cost cache coherency maintenance done by the CPU.
>> +	 */
>> +#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
>> +	defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
>> +	defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
>> +
>> +	if (!of_property_read_bool(np, "dma-coherent"))
>> +		pr_warn("Assuming cache coherent DMA transactions, no 'dma-coherent' node supplied\n");
>
> Why do you need this property at all, if it is allways dma-coherent? Are
> you supporting dma-noncoherent somewhere?

It's just a sanity check that the DT is well-formed.

Since the dma-coherent property is interpreted by common code, it's
not up to hv to change the default for the platform. I'm not sure
if the presence of CONFIG_ARCH_HAS_SYNC_DMA_* options is the correct
check to determine that an architecture defaults to noncoherent
though, as the function may be needed to do something else.

The global "dma_default_coherent' may be a better thing to check
for. This is e.g. set on powerpc64, riscv and on specific mips
platforms, but it's never set on arm64 as far as I can tell.

     Arnd