linux-kernel - Re: [PATCH v4 05/12] PCI: brcmstb: Use swinit reset if available

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Message-ID: <CA+-6iNxa2fV2K2bRGNq4M3p3_7A+__dZm7j1sWMm6F7dgpr96w@mail.gmail.com>
Date: Mon, 29 Jul 2024 17:49:53 -0400
From: Jim Quinlan <james.quinlan@...adcom.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: linux-pci@...r.kernel.org, Nicolas Saenz Julienne <nsaenz@...nel.org>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi <lorenzo.pieralisi@....com>, 
	Cyril Brulebois <kibi@...ian.org>, Stanimir Varbanov <svarbanov@...e.de>, 
	Krzysztof Kozlowski <krzk@...nel.org>, bcm-kernel-feedback-list@...adcom.com, 
	jim2101024@...il.com, Florian Fainelli <florian.fainelli@...adcom.com>, 
	Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>, 
	Rob Herring <robh@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, 
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-rpi-kernel@...ts.infradead.org>, 
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>, 
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 05/12] PCI: brcmstb: Use swinit reset if available

On Thu, Jul 25, 2024 at 12:39 AM Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org> wrote:
>
> On Tue, Jul 16, 2024 at 05:31:20PM -0400, Jim Quinlan wrote:
> > The 7712 SOC adds a software init reset device for the PCIe HW.
> > If found in the DT node, use it.
> >
> > Signed-off-by: Jim Quinlan <james.quinlan@...adcom.com>
> > Reviewed-by: Stanimir Varbanov <svarbanov@...e.de>
> > Reviewed-by: Florian Fainelli <florian.fainelli@...adcom.com>
> > ---
> >  drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > index 92816d8d215a..4dc2ff7f3167 100644
> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -266,6 +266,7 @@ struct brcm_pcie {
> >       struct reset_control    *rescal;
> >       struct reset_control    *perst_reset;
> >       struct reset_control    *bridge;
> > +     struct reset_control    *swinit;
>
> Same comment as previous patch.
>
> >       int                     num_memc;
> >       u64                     memc_size[PCIE_BRCM_MAX_MEMC];
> >       u32                     hw_rev;
> > @@ -1633,12 +1634,27 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> >       if (IS_ERR(pcie->bridge))
> >               return PTR_ERR(pcie->bridge);
> >
> > +     pcie->swinit = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit");
> > +     if (IS_ERR(pcie->swinit))
> > +             return PTR_ERR(pcie->swinit);
> > +
> >       ret = clk_prepare_enable(pcie->clk);
> >       if (ret) {
> >               dev_err(&pdev->dev, "could not enable clock\n");
> >               return ret;
> >       }
> >
> > +     ret = reset_control_assert(pcie->swinit);
> > +     if (ret) {
> > +             dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n");
> > +             goto clk_out;
> > +     }
>
> No delay required?

Unfortunately I am waiting for HW to answer this.

Regards,
Jim Quinlan
Broadcom STB/CM
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

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