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Message-ID: <172224658162.2215.14940628528309190335.tip-bot2@tip-bot2>
Date: Mon, 29 Jul 2024 09:49:41 -0000
From: tip-bot2 for Marek Behún <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: kabel@...nel.org, Thomas Gleixner <tglx@...utronix.de>, x86@...nel.org,
 linux-kernel@...r.kernel.org, maz@...nel.org
Subject:
 [tip: irq/core] irqchip/armada-370-xp: Rename variable for consistency

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     e827b6cb64b412a6b52e5fc0f453013ac98032f6
Gitweb:        https://git.kernel.org/tip/e827b6cb64b412a6b52e5fc0f453013ac98032f6
Author:        Marek Behún <kabel@...nel.org>
AuthorDate:    Thu, 11 Jul 2024 18:09:04 +02:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Mon, 29 Jul 2024 10:57:24 +02:00

irqchip/armada-370-xp: Rename variable for consistency

Rename the variable holding the cause register to "cause" in
mpic_handle_cascade_irq().

Signed-off-by: Marek Behún <kabel@...nel.org>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Link: https://lore.kernel.org/all/20240711160907.31012-8-kabel@kernel.org

---
 drivers/irqchip/irq-armada-370-xp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index c1085c7..29ce6fe 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -633,15 +633,15 @@ static inline void mpic_handle_ipi_irq(void) {}
 static void mpic_handle_cascade_irq(struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_desc_get_chip(desc);
-	unsigned long irqmap, irqsrc, cpuid;
+	unsigned long cause, irqsrc, cpuid;
 	irq_hw_number_t i;
 
 	chained_irq_enter(chip, desc);
 
-	irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE);
+	cause = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE);
 	cpuid = cpu_logical_map(smp_processor_id());
 
-	for_each_set_bit(i, &irqmap, BITS_PER_LONG) {
+	for_each_set_bit(i, &cause, BITS_PER_LONG) {
 		irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(i));
 
 		/* Check if the interrupt is not masked on current CPU.

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