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Message-ID:
<IA1PR20MB4953E36FD6384F3A4E7AAD0BBBB72@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Mon, 29 Jul 2024 08:24:15 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Chen Wang <unicorn_wang@...look.com>,
Inochi Amaoto <inochiama@...look.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Jisheng Zhang <jszhang@...nel.org>
Cc: devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: sophgo: Add sdhci0 configuration for
Huanshan Pi
On Thu, Jul 25, 2024 at 02:41:28PM GMT, Chen Wang wrote:
>
> On 2024/7/23 10:18, Inochi Amaoto wrote:
> > Add configuration for sdhci0 for Huanshan Pi to support sd card.
>
> Huanshan -> Huashan
>
> Others LGTM.
>
> Reviewed-by: Chen Wang <unicorn_wang@...look.com>
>
> Thanks,
>
> Chen
>
Thanks, I will sed it when applying the patch.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@...look.com>
> > ---
> > arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> > index aa361f3a86bb..7b5f57853690 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> > +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> > @@ -43,6 +43,15 @@ &osc {
> > clock-frequency = <25000000>;
> > };
> >
> > +&sdhci0 {
> > + status = "okay";
> > + bus-width = <4>;
> > + no-1-8-v;
> > + no-mmc;
> > + no-sdio;
> > + disable-wp;
> > +};
> > +
> > &uart0 {
> > status = "okay";
> > };
> > --
> > 2.45.2
> >
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