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Message-Id: <20240729-clk-u64-v2-2-ffa62ee437e6@nxp.com>
Date: Mon, 29 Jul 2024 10:30:53 +0800
From: "Peng Fan (OSS)" <peng.fan@....nxp.com>
To: Rob Herring <robh@...nel.org>, Saravana Kannan <saravanak@...gle.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Luca Ceresoli <luca.ceresoli@...tlin.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, Peng Fan <peng.fan@....com>
Subject: [PATCH v2 2/2] clk: clk-conf: support assigned-clock-rates-u64
From: Peng Fan <peng.fan@....com>
i.MX95 System Management Control Firmware(SCMI) manages the clock
function, it exposes PLL VCO which could support up to 5GHz rate that
exceeds UINT32_MAX. So add assigned-clock-rates-u64 support
to set rate that exceeds UINT32_MAX.
Signed-off-by: Peng Fan <peng.fan@....com>
---
drivers/clk/clk-conf.c | 104 ++++++++++++++++++++++++++++++++++---------------
1 file changed, 73 insertions(+), 31 deletions(-)
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 058420562020..37b72600b296 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -78,47 +78,89 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
return rc;
}
-static int __set_clk_rates(struct device_node *node, bool clk_supplier)
+static int __set_clk_rate(struct device_node *node, bool clk_supplier, int index,
+ unsigned long rate)
{
struct of_phandle_args clkspec;
- int rc, index = 0;
struct clk *clk;
- u32 rate;
+ int rc;
- of_property_for_each_u32(node, "assigned-clock-rates", rate) {
- if (rate) {
- rc = of_parse_phandle_with_args(node, "assigned-clocks",
+ rc = of_parse_phandle_with_args(node, "assigned-clocks",
"#clock-cells", index, &clkspec);
- if (rc < 0) {
- /* skip empty (null) phandles */
- if (rc == -ENOENT)
- continue;
- else
- return rc;
- }
- if (clkspec.np == node && !clk_supplier) {
- of_node_put(clkspec.np);
- return 0;
- }
+ if (rc < 0)
+ return rc;
- clk = of_clk_get_from_provider(&clkspec);
- of_node_put(clkspec.np);
- if (IS_ERR(clk)) {
- if (PTR_ERR(clk) != -EPROBE_DEFER)
- pr_warn("clk: couldn't get clock %d for %pOF\n",
- index, node);
- return PTR_ERR(clk);
+ if (clkspec.np == node && !clk_supplier) {
+ of_node_put(clkspec.np);
+ return 1;
+ }
+
+ clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+ if (IS_ERR(clk)) {
+ if (PTR_ERR(clk) != -EPROBE_DEFER)
+ pr_warn("clk: couldn't get clock %d for %pOF\n",
+ index, node);
+ return PTR_ERR(clk);
+ }
+
+ rc = clk_set_rate(clk, rate);
+ if (rc < 0)
+ pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n",
+ __clk_get_name(clk), rate, rc, clk_get_rate(clk));
+ clk_put(clk);
+
+ return 0;
+}
+
+static int __set_clk_rates(struct device_node *node, bool clk_supplier)
+{
+ int rc, index = 0;
+ u64 rate;
+ u32 rate_32;
+ bool is_rate_32 = false;
+
+ if (!of_find_property(node, "assigned-clock-rates-u64", NULL))
+ is_rate_32 = true;
+
+ if (is_rate_32) {
+ of_property_for_each_u32(node, "assigned-clock-rates", rate_32) {
+ if (rate_32) {
+ rc = __set_clk_rate(node, clk_supplier, index, rate_32);
+
+ if (rc == 1 && !clk_supplier)
+ return 0;
+
+ if (rc < 0) {
+ /* skip empty (null) phandles */
+ if (rc == -ENOENT)
+ continue;
+ else
+ return rc;
+ }
}
+ index++;
+ }
+ } else {
+ of_property_for_each_u64(node, "assigned-clock-rates-u64", rate) {
+ if (rate) {
+ rc = __set_clk_rate(node, clk_supplier, index, rate);
- rc = clk_set_rate(clk, rate);
- if (rc < 0)
- pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",
- __clk_get_name(clk), rate, rc,
- clk_get_rate(clk));
- clk_put(clk);
+ if (rc == 1 && !clk_supplier)
+ return 0;
+
+ if (rc < 0) {
+ /* skip empty (null) phandles */
+ if (rc == -ENOENT)
+ continue;
+ else
+ return rc;
+ }
+ }
+ index++;
}
- index++;
}
+
return 0;
}
--
2.37.1
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