linux-kernel - [tip: irq/core] irqchip/armada-370-xp: Don't read number of supported interrupts multiple times

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Message-ID: <172233960054.2215.13758750324090897274.tip-bot2@tip-bot2>
Date: Tue, 30 Jul 2024 11:40:00 -0000
From: tip-bot2 for Marek Behún <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: kabel@...nel.org, Thomas Gleixner <tglx@...utronix.de>,
 Andrew Lunn <andrew@...n.ch>, ilpo.jarvinen@...ux.intel.com, x86@...nel.org,
 linux-kernel@...r.kernel.org, maz@...nel.org
Subject: [tip: irq/core] irqchip/armada-370-xp: Don't read number of supported
 interrupts multiple times

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     5ecafc9a640f7c1e5690375cf3a82848d669abb9
Gitweb:        https://git.kernel.org/tip/5ecafc9a640f7c1e5690375cf3a82848d669abb9
Author:        Marek Behún <kabel@...nel.org>
AuthorDate:    Thu, 11 Jul 2024 13:57:45 +02:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Tue, 30 Jul 2024 13:35:47 +02:00

irqchip/armada-370-xp: Don't read number of supported interrupts multiple times

Use mpic_domain::hwirq_max at runtime instead of reading the same value
over and over from the MPIC_INT_CONTROL register.

Signed-off-by: Marek Behún <kabel@...nel.org>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Andrew Lunn <andrew@...n.ch>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Link: https://lore.kernel.org/all/20240711115748.30268-8-kabel@kernel.org


---
 drivers/irqchip/irq-armada-370-xp.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 2758834..e43eb26 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -494,13 +494,7 @@ static int mpic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
 static void mpic_smp_cpu_init(void)
 {
-	u32 control;
-	int nr_irqs;
-
-	control = readl(main_int_base + MPIC_INT_CONTROL);
-	nr_irqs = (control >> 2) & 0x3ff;
-
-	for (int i = 0; i < nr_irqs; i++)
+	for (int i = 0; i < mpic_domain->hwirq_max; i++)
 		writel(i, per_cpu_int_base + MPIC_INT_SET_MASK);
 
 	if (!mpic_is_ipi_available())
@@ -706,10 +700,9 @@ static int mpic_suspend(void)
 static void mpic_resume(void)
 {
 	bool src0, src1;
-	int nirqs;
+
 	/* Re-enable interrupts */
-	nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff;
-	for (irq_hw_number_t irq = 0; irq < nirqs; irq++) {
+	for (irq_hw_number_t irq = 0; irq < mpic_domain->hwirq_max; irq++) {
 		struct irq_data *data;
 		unsigned int virq;