lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20240730-k1-01-basic-dt-v5-2-98263aae83be@gentoo.org>
Date: Tue, 30 Jul 2024 00:28:05 +0000
From: Yixun Lan <dlan@...too.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Yangyu Chen <cyy@...self.name>, Yixun Lan <dlan@...too.org>, 
 Daniel Lezcano <daniel.lezcano@...aro.org>, 
 Thomas Gleixner <tglx@...utronix.de>, 
 Samuel Holland <samuel.holland@...ive.com>, 
 Anup Patel <anup@...infault.org>, 
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
 Jiri Slaby <jirislaby@...nel.org>, Lubomir Rintel <lkundrak@...sk>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org, 
 Jesse Taube <jesse@...osinc.com>, Jisheng Zhang <jszhang@...nel.org>, 
 Inochi Amaoto <inochiama@...look.com>, Icenowy Zheng <uwu@...nowy.me>, 
 Meng Zhang <zhangmeng.kevin@...cemit.com>, 
 Meng Zhang <kevin.z.m@...mail.com>, 
 Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v5 02/10] dt-bindings: riscv: Add SpacemiT X60 compatibles

From: Yangyu Chen <cyy@...self.name>

The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1
SoC.

Link: https://www.spacemit.com/en/spacemit-x60-core/
Signed-off-by: Yangyu Chen <cyy@...self.name>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Signed-off-by: Yixun Lan <dlan@...too.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 8edc8261241ad..acb5b9ba6f049 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -46,6 +46,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x60
               - thead,c906
               - thead,c908
               - thead,c910

-- 
2.45.2


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ