linux-kernel - [PATCH 2/3] riscv: dts: starfive: jh7110: Add sys-syscon property to usbphy0

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Message-ID: <b785c849ebae7040c83a2d0c097064e5a451480a.1722457123.git.jan.kiszka@siemens.com>
Date: Wed, 31 Jul 2024 22:18:42 +0200
From: Jan Kiszka <jan.kiszka@...mens.com>
To: Minda Chen <minda.chen@...rfivetech.com>,
	Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>
Cc: linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>
Subject: [PATCH 2/3] riscv: dts: starfive: jh7110: Add sys-syscon property to usbphy0

From: Jan Kiszka <jan.kiszka@...mens.com>

Allows the PHY to connect to its USB controller.

Signed-off-by: Jan Kiszka <jan.kiszka@...mens.com>
---
CC: Rob Herring <robh@...nel.org>
CC: Krzysztof Kozlowski <krzk+dt@...nel.org>
CC: Conor Dooley <conor+dt@...nel.org>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0d8339357bad..0c0b66a69065 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -606,6 +606,7 @@ usbphy0: phy@...00000 {
 				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 			clock-names = "125m", "app_125m";
 			#phy-cells = <0>;
+			starfive,sys-syscon = <&sys_syscon 0x18>;
 		};
 
 		pciephy0: phy@...10000 {
-- 
2.43.0