linux-kernel - Re: [PATCH 0/3] x86: Make 5-level paging support unconditional for x86-64

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Message-ID: <87wml16hye.ffs@tglx>
Date: Wed, 31 Jul 2024 11:15:05 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: 20240621164406.256314-1-kirill.shutemov@...ux.intel.com,
 kirill.shutemov@...ux.intel.com
Cc: ardb@...nel.org, bp@...en8.de, brijesh.singh@....com, corbet@....net,
 dave.hansen@...ux.intel.com, hpa@...or.com, jan.kiszka@...mens.com,
 jgross@...e.com, kbingham@...nel.org, linux-doc@...r.kernel.org,
 linux-efi@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-mm@...ck.org, luto@...nel.org, michael.roth@....com,
 mingo@...hat.com, peterz@...radead.org, rick.p.edgecombe@...el.com,
 sandipan.das@....com, thomas.lendacky@....com, x86@...nel.org
Subject: Re: [PATCH 0/3] x86: Make 5-level paging support unconditional for
 x86-64

On Wed, Jul 31 2024 at 14:27, Shivank Garg wrote:
> lmbench:lat_pagefault: Metric- page-fault time (us) - Lower is better
>                 4-Level PT              5-Level PT		% Change
> THP-never       Mean:0.4068             Mean:0.4294		5.56
>                 95% CI:0.4057-0.4078    95% CI:0.4287-0.4302
>
> THP-Always      Mean: 0.4061            Mean: 0.4288		% Change
>                 95% CI: 0.4051-0.4071   95% CI: 0.4281-0.4295	5.59
>
> Inference:
> 5-level page table shows increase in page-fault latency but it does
> not significantly impact other benchmarks.

5% regression on lmbench is a NONO.

5-level page tables add a cost in every hardware page table walk. That's
a matter of fact and there is absolutely no reason to inflict this cost
on everyone.

The solution to this to make the 5-level mechanics smarter by evaluating
whether the machine has enough memory to require 5-level tables and
select the depth at boot time.

Thanks,

        tglx