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Message-Id: <20240731111951.6999-1-quic_anshar@quicinc.com>
Date: Wed, 31 Jul 2024 16:49:51 +0530
From: Ankit Sharma <quic_anshar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org, richardcochran@...il.com
Cc: Ankit Sharma <quic_anshar@...cinc.com>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org
Subject: [PATCH V1] arm64: dts: qcom: sa8775p: Add capacity and DPC properties
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn is used by EAS to take
placement decisions.
Signed-off-by: Ankit Sharma <quic_anshar@...cinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 3bb609c9d2ec..ab15556e0647 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -68,6 +68,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -88,6 +90,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_1>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -103,6 +107,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -118,6 +124,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -133,6 +141,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_4>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -154,6 +164,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_5>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -169,6 +181,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_6>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -184,6 +198,8 @@
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_7>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
--
2.17.1
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