linux-kernel - Re: [PATCH] arm64/mm: Avoid direct referencing page table enties in map

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20240801144643.GA4980@willie-the-truck>
Date: Thu, 1 Aug 2024 15:46:43 +0100
From: Will Deacon <will@...nel.org>
To: Ryan Roberts <ryan.roberts@....com>
Cc: Anshuman Khandual <anshuman.khandual@....com>,
	linux-arm-kernel@...ts.infradead.org,
	Catalin Marinas <catalin.marinas@....com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64/mm: Avoid direct referencing page table enties in
 map_range()

On Thu, Aug 01, 2024 at 03:07:31PM +0100, Ryan Roberts wrote:
> diff --git a/arch/arm64/kernel/pi/map_range.c b/arch/arm64/kernel/pi/map_range.c
> index 5410b2cac5907..3f6c5717ff782 100644
> --- a/arch/arm64/kernel/pi/map_range.c
> +++ b/arch/arm64/kernel/pi/map_range.c
> @@ -55,13 +55,14 @@ void __init map_range(u64 *pte, u64 start, u64 end, u64 pa, pgprot_t prot,
>                          * This chunk needs a finer grained mapping. Create a
>                          * table mapping if necessary and recurse.
>                          */
> -                       if (pte_none(*tbl)) {
> -                               *tbl = __pte(__phys_to_pte_val(*pte) |
> -                                            PMD_TYPE_TABLE | PMD_TABLE_UXN);
> +                       if (pte_none(__ptep_get(tbl))) {
> +                               __set_pte_nosync(tbl,
> +                                            __pte(__phys_to_pte_val(*pte) |
> +                                            PMD_TYPE_TABLE | PMD_TABLE_UXN));
>                                 *pte += PTRS_PER_PTE * sizeof(pte_t);
>                         }
>                         map_range(pte, start, next, pa, prot, level + 1,
> -                                 (pte_t *)(__pte_to_phys(*tbl) + va_offset),
> +                                 (pte_t *)(__pte_to_phys(__ptep_get(tbl)) + va_offset),
>                                   may_use_cont, va_offset);
>                 } else {
>                         /*
> @@ -79,7 +80,7 @@ void __init map_range(u64 *pte, u64 start, u64 end, u64 pa, pgprot_t prot,
>                                 protval &= ~PTE_CONT;
>  
>                         /* Put down a block or page mapping */
> -                       *tbl = __pte(__phys_to_pte_val(pa) | protval);
> +                       __set_pte_nosync(tbl, __pte(__phys_to_pte_val(pa) | protval));
>                 }
>                 pa += next - start;
>                 start = next;

That looks good to me!

Will