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Message-Id: <20240801-th1520-clk-dts-v1-1-71077a0614b8@pdp7.com>
Date: Thu, 01 Aug 2024 11:38:05 -0700
From: Drew Fustini <drew@...7.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Thomas Bonnefille <thomas.bonnefille@...tlin.com>,
Kanak Shilledar <kanakshilledar@...il.com>,
Jisheng Zhang <jszhang@...nel.org>, Guo Ren <guoren@...nel.org>,
Fu Wei <wefu@...hat.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Drew Fustini <drew@...7.com>,
Drew Fustini <dfustini@...storrent.com>
Subject: [PATCH 1/6] riscv: dts: thead: Add TH1520 AP_SUBSYS clock
controller
From: Drew Fustini <dfustini@...storrent.com>
Add node for the AP_SUBSYS clock controller on the T-Head TH1520 SoC.
Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@...storrent.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index aa703da30fc3..25ef5ee729e6 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/thead,th1520-clk-ap.h>
/ {
compatible = "thead,th1520";
@@ -419,6 +420,13 @@ uart2: serial@...c010000 {
status = "disabled";
};
+ clk: clock-controller@...f010000 {
+ compatible = "thead,th1520-clk-ap";
+ reg = <0xff 0xef010000 0x0 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
dmac0: dma-controller@...fc00000 {
compatible = "snps,axi-dma-1.01a";
reg = <0xff 0xefc00000 0x0 0x1000>;
--
2.34.1
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