linux-kernel - [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes

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Message-Id: <20240801-th1520-clk-dts-v1-5-71077a0614b8@pdp7.com>
Date: Thu, 01 Aug 2024 11:38:09 -0700
From: Drew Fustini <drew@...7.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>, 
 Thomas Bonnefille <thomas.bonnefille@...tlin.com>, 
 Kanak Shilledar <kanakshilledar@...il.com>, 
 Jisheng Zhang <jszhang@...nel.org>, Guo Ren <guoren@...nel.org>, 
 Fu Wei <wefu@...hat.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, Drew Fustini <drew@...7.com>, 
 Drew Fustini <dfustini@...storrent.com>
Subject: [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes

From: Drew Fustini <dfustini@...storrent.com>

Add clock property to TH1520 gpio controller nodes. These clock gates
refer to corresponding enable bits in the peripheral clock gate control
register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the
TH1520 System User Manual.

Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@...storrent.com>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 6ea5cabbcf60..5f4f94ca9cc7 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -327,6 +327,7 @@ gpio2: gpio@...7f34000 {
 			reg = <0xff 0xe7f34000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			clocks = <&clk CLK_GPIO2>;
 
 			portc: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
@@ -345,6 +346,7 @@ gpio3: gpio@...7f38000 {
 			reg = <0xff 0xe7f38000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			clocks = <&clk CLK_GPIO3>;
 
 			portd: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
@@ -363,6 +365,7 @@ gpio0: gpio@...c005000 {
 			reg = <0xff 0xec005000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			clocks = <&clk CLK_GPIO0>;
 
 			porta: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";
@@ -381,6 +384,7 @@ gpio1: gpio@...c006000 {
 			reg = <0xff 0xec006000 0x0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			clocks = <&clk CLK_GPIO1>;
 
 			portb: gpio-controller@0 {
 				compatible = "snps,dw-apb-gpio-port";

-- 
2.34.1