linux-kernel - [PATCH v5 0/5] Refine i.MX8QM SATA based on generic PHY callbacks

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Message-Id: <1722581213-15221-1-git-send-email-hongxing.zhu@nxp.com>
Date: Fri,  2 Aug 2024 14:46:48 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	shawnguo@...nel.org,
	l.stach@...gutronix.de
Cc: hongxing.zhu@....com,
	devicetree@...r.kernel.org,
	linux-pci@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	kernel@...gutronix.de,
	imx@...ts.linux.dev
Subject: [PATCH v5 0/5] Refine i.MX8QM SATA based on generic PHY callbacks

V5 main changes:
Thanks for Niklas' kind help.
- Drop 32bit DMA limit commit, since the "dma-ranges" of DT can overcome
  this limitation.

V4 main changes:
Thanks for Niklas' comments.
- Update the commit message in #2 patch of v4.
- Split the clean up unrelated codes to #3 and #4 of v4.
- Remove the Cc: stable@...r.kernel.org and Fixes tag in #5 of v4.

V3 main changes:
- Use GENMASK() macro to define the _MASK.
- Refine the macro names.

V2 main changes:
- Add Rob's reviewed-by in the binding patch.
- Re-name the error out lables and new RXWM macro more descriptive.
- In #3 patch, add one fix tag, and CC stable kernel.

Based on i.MX8QM HSIO PHY driver, refine i.MX8QM SATA driver by using PHY
interface.

[PATCH v5 1/5] dt-bindings: ata: Add i.MX8QM AHCI compatible string
[PATCH v5 2/5] ata: ahci_imx: Clean up code by using i.MX8Q HSIO PHY
[PATCH v5 3/5] ata: ahci_imx: AHB clock rate setting is not required
[PATCH v5 4/5] ata: ahci_imx: Enlarge RX water mark for i.MX8QM SATA
[PATCH v5 5/5] ata: ahci_imx: Correct the email address

Documentation/devicetree/bindings/ata/imx-sata.yaml |  47 +++++++++++
drivers/ata/ahci_imx.c                              | 403 +++++++++++++++++++++++------------------------------------------------------------------
2 files changed, 152 insertions(+), 298 deletions(-)