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Message-ID: <3483951.iGylCHCCq3@bagend>
Date: Sun, 04 Aug 2024 13:27:35 +0200
From: Diederik de Haas <didi.debian@...ow.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, Chris Morgan <macromorgan@...mail.com>,
Jonas Karlman <jonas@...boo.se>, Tim Lunn <tim@...thertop.org>,
Andy Yan <andyshrk@....com>, Muhammed Efe Cetin <efectn@...tonmail.com>,
Jagan Teki <jagan@...eble.ai>, Dragan Simic <dsimic@...jaro.org>,
Ondrej Jirman <megi@....cz>, linux-rockchip@...ts.infradead.org
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-serial@...r.kernel.org, Yao Zi <ziyao@...root.org>,
Yao Zi <ziyao@...root.org>
Subject: Re: [PATCH 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC
On Saturday, 3 August 2024 14:55:10 CEST Yao Zi wrote:
> + gic: interrupt-controller@...01000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x0 0xfed01000 0 0x1000>,
> + <0x0 0xfed02000 0 0x2000>,
> + <0x0 0xfed04000 0 0x2000>,
> + <0x0 0xfed06000 0 0x2000>;
> + interrupts = <GIC_PPI 9
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + uart0: serial@...f0000 {
> + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xff9f0000 0x0 0x100>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clock-frequency = <24000000>;
> + status = "disabled";
> + };
The properties should be sorted as follows:
- compatible
- reg
- <other properties sorted alphabetically>
- status
This also applies to the other blocks which I didn't quote.
Cheers,
Diederik
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