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Message-ID: <Zq-AlANMrNCf5xCK@ziyaolaptop.my.domain>
Date: Sun, 4 Aug 2024 21:22:28 +0800
From: Yao Zi <ziyao@...root.org>
To: Diederik de Haas <didi.debian@...ow.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Chris Morgan <macromorgan@...mail.com>,
Jonas Karlman <jonas@...boo.se>, Tim Lunn <tim@...thertop.org>,
Andy Yan <andyshrk@....com>,
Muhammed Efe Cetin <efectn@...tonmail.com>,
Jagan Teki <jagan@...eble.ai>, Dragan Simic <dsimic@...jaro.org>,
Ondrej Jirman <megi@....cz>, linux-rockchip@...ts.infradead.org
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC
On Sun, Aug 04, 2024 at 01:27:35PM +0200, Diederik de Haas wrote:
> On Saturday, 3 August 2024 14:55:10 CEST Yao Zi wrote:
> > + gic: interrupt-controller@...01000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + #address-cells = <0>;
> > + interrupt-controller;
> > + reg = <0x0 0xfed01000 0 0x1000>,
> > + <0x0 0xfed02000 0 0x2000>,
> > + <0x0 0xfed04000 0 0x2000>,
> > + <0x0 0xfed06000 0 0x2000>;
> > + interrupts = <GIC_PPI 9
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> > + };
> > +
> > + uart0: serial@...f0000 {
> > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> > + reg = <0x0 0xff9f0000 0x0 0x100>;
> > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clock-frequency = <24000000>;
> > + status = "disabled";
> > + };
>
> The properties should be sorted as follows:
> - compatible
> - reg
> - <other properties sorted alphabetically>
> - status
>
> This also applies to the other blocks which I didn't quote.
Thanks, will be fixed in next revision.
Best regards,
Yao Zi
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