linux-kernel - Re: [PATCH v2 0/8] PCI: Enable Power and configure the QPS615 PCIe switch

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Message-ID: <a1981c4d-a81e-ecb3-bb81-b77d9c14789a@quicinc.com>
Date: Mon, 5 Aug 2024 09:48:43 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
        Lorenzo Pieralisi
	<lpieralisi@...nel.org>,
        Krzysztof Wilczyński
	<kw@...ux.com>,
        Rob Herring <robh@...nel.org>, Bjorn Helgaas
	<bhelgaas@...gle.com>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        <cros-qcom-dts-watchers@...omium.org>,
        Bartosz Golaszewski <brgl@...ev.pl>, Jingoo Han <jingoohan1@...il.com>,
        Manivannan Sadhasivam
	<manivannan.sadhasivam@...aro.org>
CC: <andersson@...nel.org>, <quic_vbadigan@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-pci@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        "Bartosz
 Golaszewski" <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v2 0/8] PCI: Enable Power and configure the QPS615 PCIe
 switch



On 8/4/2024 2:27 PM, Krzysztof Kozlowski wrote:
> On 03/08/2024 05:22, Krishna chaitanya chundru wrote:
>> QPS615 is the PCIe switch which has one upstream and three downstream
>> ports. One of the downstream ports is used as endpoint device of Ethernet
>> MAC. Other two downstream ports are supposed to connect to external
>> device. One Host can connect to QPS615 by upstream port.
>>
>> QPS615 switch power is controlled by the GPIO's. After powering on
>> the switch will immediately participate in the link training. if the
>> host is also ready by that time PCIe link will established.
>>
>> The QPS615 needs to configured certain parameters like de-emphasis,
>> disable unused port etc before link is established.
>>
>> The device tree properties are parsed per node under pci-pci bridge in the
>> devicetree. Each node has unique bdf value in the reg property, driver
>> uses this bdf to differentiate ports, as there are certain i2c writes to
>> select particulat port.
>>   
>> As the controller starts link training before the probe of pwrctl driver,
>> the PCIe link may come up before configuring the switch itself.
>> To avoid this introduce two functions in pci_ops to start_link() &
>> stop_link() which will disable the link training if the PCIe link is
>> not up yet.
>>
>> Now PCI pwrctl device is the child of the pci-pcie bridge, if we want
>> to enable the suspend resume for pwrctl device there may be issues
>> since pci bridge will try to access some registers in the config which
>> may cause timeouts or Un clocked access as the power can be removed in
>> the suspend of pwrctl driver.
>>
>> To solve this make PCIe controller as parent to the pci pwr ctrl driver
>> and create devlink between host bridge and pci pwrctl driver so that
>> pci pwrctl driver will go suspend only after all the PCIe devices went
>> to suspend.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> ---
>> Changes in V1:
>> - Fix the code as per the comments given.
> 
> You did not implement the comments so such changelog is rather a joke.
> Respond to each comment from v1 and acknowledge it.
> 
> Then write detailed changelog.
> 
> Best regards,
> Krzysztof
> 
I will write a detailed changelog from v3 onwards spare me for this time.

- Krishna Chaitanya.