linux-kernel - Re: [PATCH v2 0/8] PCI: Enable Power and configure the QPS615 PCIe switch

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ae069a46-a1f4-e847-8b9b-81ca1329d2a3@quicinc.com>
Date: Mon, 5 Aug 2024 10:04:54 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Rob Herring
	<robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Konrad Dybcio
	<konrad.dybcio@...aro.org>,
        <cros-qcom-dts-watchers@...omium.org>,
        "Bartosz
 Golaszewski" <brgl@...ev.pl>,
        Jingoo Han <jingoohan1@...il.com>,
        "Manivannan
 Sadhasivam" <manivannan.sadhasivam@...aro.org>
CC: <andersson@...nel.org>, <quic_vbadigan@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-pci@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        "Bartosz
 Golaszewski" <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v2 0/8] PCI: Enable Power and configure the QPS615 PCIe
 switch



On 8/3/2024 8:52 AM, Krishna chaitanya chundru wrote:
> QPS615 is the PCIe switch which has one upstream and three downstream
> ports. One of the downstream ports is used as endpoint device of Ethernet
> MAC. Other two downstream ports are supposed to connect to external
> device. One Host can connect to QPS615 by upstream port.
> 
> QPS615 switch power is controlled by the GPIO's. After powering on
> the switch will immediately participate in the link training. if the
> host is also ready by that time PCIe link will established.
> 
> The QPS615 needs to configured certain parameters like de-emphasis,
> disable unused port etc before link is established.
> 
> The device tree properties are parsed per node under pci-pci bridge in the
> devicetree. Each node has unique bdf value in the reg property, driver
> uses this bdf to differentiate ports, as there are certain i2c writes to
> select particulat port.
>   
> As the controller starts link training before the probe of pwrctl driver,
> the PCIe link may come up before configuring the switch itself.
> To avoid this introduce two functions in pci_ops to start_link() &
> stop_link() which will disable the link training if the PCIe link is
> not up yet.
> 
> Now PCI pwrctl device is the child of the pci-pcie bridge, if we want
> to enable the suspend resume for pwrctl device there may be issues
> since pci bridge will try to access some registers in the config which
> may cause timeouts or Un clocked access as the power can be removed in
> the suspend of pwrctl driver.
> 
> To solve this make PCIe controller as parent to the pci pwr ctrl driver
> and create devlink between host bridge and pci pwrctl driver so that
> pci pwrctl driver will go suspend only after all the PCIe devices went
> to suspend.
> 
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> ---
> Changes in V1:
> - Fix the code as per the comments given.
changes in v1:
- Instead of referencing whole i2c-bus add i2c-client node and reference 
it (Dmitry)
- Change the regulator's as per the schematics as per offline review
(bjorn Andresson)
- Remove additional host check in bus.c (Bart)
- For stop_link op change return type from int to void (Bart)
- Remove firmware based approach for configuring sequence as suggested
by multiple reviewers.
- Introduce new dt-properties for the switch to configure the switch
as we are replacing the firmware based approach.
- The downstream ports add properties in the child nodes which will
represented in PCIe hierarchy format.
- Removed D3cold D0 sequence in suspend resume for now as it needs
separate discussion.

- Krishna Chaitanya.
> - Removed D3cold D0 sequence in suspend resume for now as it needs
>    seperate discussion.
> - change to dt approach for configuring the switch instead of request_firmware() approach
> - Link to v1: https://lore.kernel.org/linux-pci/20240626-qps615-v1-4-2ade7bd91e02@quicinc.com/T/
> ---
> 
> ---
> Krishna chaitanya chundru (8):
>        dt-bindings: PCI: Add binding for qps615
>        dt-bindings: trivial-devices: Add qcom,qps615
>        arm64: dts: qcom: qcs6490-rb3gen2: Add node for qps615
>        PCI: Change the parent to correctly represent pcie hierarchy
>        PCI: Add new start_link() & stop_link function ops
>        PCI: dwc: Add support for new pci function op
>        PCI: qcom: Add support for host_stop_link() & host_start_link()
>        PCI: pwrctl: Add power control driver for qps615
> 
>   .../devicetree/bindings/pci/qcom,qps615.yaml       | 191 ++++++
>   .../devicetree/bindings/trivial-devices.yaml       |   2 +
>   arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts       | 121 ++++
>   arch/arm64/boot/dts/qcom/sc7280.dtsi               |   2 +-
>   drivers/pci/bus.c                                  |   3 +-
>   drivers/pci/controller/dwc/pcie-designware-host.c  |  18 +
>   drivers/pci/controller/dwc/pcie-designware.h       |  16 +
>   drivers/pci/controller/dwc/pcie-qcom.c             |  39 ++
>   drivers/pci/pwrctl/Kconfig                         |   7 +
>   drivers/pci/pwrctl/Makefile                        |   1 +
>   drivers/pci/pwrctl/core.c                          |   9 +-
>   drivers/pci/pwrctl/pci-pwrctl-qps615.c             | 638 +++++++++++++++++++++
>   include/linux/pci.h                                |   2 +
>   13 files changed, 1046 insertions(+), 3 deletions(-)
> ---
> base-commit: 1722389b0d863056d78287a120a1d6cadb8d4f7b
> change-id: 20240727-qps615-e2894a38d36f
> 
> Best regards,