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Message-ID: <20240806154415.wrsqxgyqdi2y4ae6@candy>
Date: Tue, 6 Aug 2024 10:44:15 -0500
From: Nishanth Menon <nm@...com>
To: Kevin Hilman <khilman@...libre.com>
CC: Tero Kristo <kristo@...nel.org>, Santosh Shilimkar <ssantosh@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
Akashdeep Kaur <a-kaur@...com>,
Markus Schneider-Pargmann <msp@...libre.com>,
Vibhore Vardhan <vibhore@...com>, Dhruva Gole <d-gole@...com>
Subject: Re: [PATCH v3] firmware: ti_sci: add CPU latency constraint
management
On 14:42-20240802, Kevin Hilman wrote:
> During system-wide suspend, check if any of the CPUs have PM QoS
> resume latency constraints set. If so, set TI SCI constraint.
>
> TI SCI has a single system-wide latency constraint, so use the max of
> any of the CPU latencies as the system-wide value.
>
> Note: DM firmware clears all constraints at resume time, so
> constraints need to be checked/updated/sent at each system suspend.
>
> Co-developed-by: Vibhore Vardhan <vibhore@...com>
> Signed-off-by: Vibhore Vardhan <vibhore@...com>
> Signed-off-by: Kevin Hilman <khilman@...libre.com>
> Reviewed-by: Dhruva Gole <d-gole@...com>
> Signed-off-by: Dhruva Gole <d-gole@...com>
> ---
> Depends on the TI SCI series where support for the constraints APIs
> are added:
> https://lore.kernel.org/r/20240801195422.2296347-1-msp@baylibre.com
>
Unless there is a reason to maintain this patch separately, Could we
add this to the mentioned series -> it is much easier to review and
merge them in one go.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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