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Message-ID: <ZrJI/aa1O4/WDl4+@lizhi-Precision-Tower-5810>
Date: Tue, 6 Aug 2024 12:02:05 -0400
From: Frank Li <Frank.li@....com>
To: carlos.song@....com
Cc: alexandre.belloni@...tlin.com, miquel.raynal@...tlin.com,
conor.culhane@...vaco.com, linux-i3c@...ts.infradead.org,
linux-kernel@...r.kernel.org, imx@...ts.linux.dev,
linux-imx@....com
Subject: Re: [PATCH 2/2] i3c: master: svc: use slow speed for first broadcast
address
On Tue, Aug 06, 2024 at 02:48:51PM +0800, carlos.song@....com wrote:
> From: Carlos Song <carlos.song@....com>
>
> I3C controller should support adjusting open drain timing for the first
> broadcast address to make I3C device working as a i2c device can see slow
> broadcast address to close its Spike Filter to change working at i3c mode.
>
> Signed-off-by: Carlos Song <carlos.song@....com>
> ---
A small nik below.
Reviewed-by: Frank Li <Frank.Li@....com>
> drivers/i3c/master/svc-i3c-master.c | 51 +++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i3c-master.c
> index 0a68fd1b81d4..4cdce25c5cf7 100644
> --- a/drivers/i3c/master/svc-i3c-master.c
> +++ b/drivers/i3c/master/svc-i3c-master.c
> @@ -212,6 +212,7 @@ struct svc_i3c_master {
> } ibi;
> struct mutex lock;
> int enabled_events;
> + u32 mctrl_config;
> };
>
> /**
> @@ -529,6 +530,54 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> +static int svc_i3c_master_set_speed(struct i3c_master_controller *m,
> + enum i3c_open_drain_speed speed)
> +{
> + struct svc_i3c_master *master = to_svc_i3c_master(m);
> + struct i3c_bus *bus = i3c_master_get_bus(&master->base);
> + unsigned long fclk_rate;
> + u32 ppbaud, odbaud, odhpp, mconfig;
> + int ret;
try keep reverse christmas tree order.
> +
> + ret = pm_runtime_resume_and_get(master->dev);
> + if (ret < 0) {
> + dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
> + return ret;
> + }
> +
> + switch (speed) {
> + case I3C_OPEN_DRAIN_SLOW_SPEED:
> + fclk_rate = clk_get_rate(master->fclk);
> + if (!fclk_rate) {
> + ret = -EINVAL;
> + goto rpm_out;
> + }
> + /*
> + * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first
> + * broadcast address is visible to all I2C/I3C devices on the I3C bus.
> + * I3C device working as a I2C device will turn off its 50ns Spike
> + * Filter to change to I3C mode.
> + */
> + mconfig = master->mctrl_config;
> + ppbaud = FIELD_GET(GENMASK(11, 8), mconfig);
> + odhpp = 0;
> + odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1;
> + mconfig &= ~GENMASK(24, 16);
> + mconfig |= SVC_I3C_MCONFIG_ODBAUD(odbaud) | SVC_I3C_MCONFIG_ODHPP(odhpp);
> + writel(mconfig, master->regs + SVC_I3C_MCONFIG);
> + break;
> + case I3C_OPEN_DRAIN_NORMAL_SPEED:
> + writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
> + break;
> + }
> +
> +rpm_out:
> + pm_runtime_mark_last_busy(master->dev);
> + pm_runtime_put_autosuspend(master->dev);
> +
> + return ret;
> +}
> +
> static int svc_i3c_master_bus_init(struct i3c_master_controller *m)
> {
> struct svc_i3c_master *master = to_svc_i3c_master(m);
> @@ -611,6 +660,7 @@ static int svc_i3c_master_bus_init(struct i3c_master_controller *m)
> SVC_I3C_MCONFIG_I2CBAUD(i2cbaud);
> writel(reg, master->regs + SVC_I3C_MCONFIG);
>
> + master->mctrl_config = reg;
> /* Master core's registration */
> ret = i3c_master_get_free_addr(m, 0);
> if (ret < 0)
> @@ -1645,6 +1695,7 @@ static const struct i3c_master_controller_ops svc_i3c_master_ops = {
> .disable_ibi = svc_i3c_master_disable_ibi,
> .enable_hotjoin = svc_i3c_master_enable_hotjoin,
> .disable_hotjoin = svc_i3c_master_disable_hotjoin,
> + .set_speed = svc_i3c_master_set_speed,
> };
>
> static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)
> --
> 2.34.1
>
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