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Message-ID:
<PAXPR04MB8459B99A43EA08ADED98DEA788BF2@PAXPR04MB8459.eurprd04.prod.outlook.com>
Date: Tue, 6 Aug 2024 14:54:01 +0000
From: Peng Fan <peng.fan@....com>
To: Frieder Schrempf <frieder.schrempf@...tron.de>, Frieder Schrempf
<frieder@...s.de>, Conor Dooley <conor+dt@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, Rob Herring <robh@...nel.org>, Sascha Hauer
<s.hauer@...gutronix.de>, Shawn Guo <shawnguo@...nel.org>
CC: Alexander Stein <alexander.stein@...tq-group.com>, Fabio Estevam
<festevam@...il.com>, Francesco Dolcini <francesco.dolcini@...adex.com>,
Gregor Herburger <gregor.herburger@...tq-group.com>, Joao Paulo Goncalves
<joao.goncalves@...adex.com>, Parthiban Nallathambi <parthiban@...umiz.com>,
Pengutronix Kernel Team <kernel@...gutronix.de>, "tharvey@...eworks.com"
<tharvey@...eworks.com>
Subject: RE: [PATCH v3 2/2] arm64: dts: Add support for Kontron i.MX93 OSM-S
SoM and BL carrier board
> Subject: Re: [PATCH v3 2/2] arm64: dts: Add support for Kontron
> i.MX93 OSM-S SoM and BL carrier board
>
> Hi Peng,
>
> thanks for reviewing!
>
> On 01.08.24 4:10 AM, Peng Fan wrote:
> >> Subject: [PATCH v3 2/2] arm64: dts: Add support for Kontron
> i.MX93
> >> OSM-S SoM and BL carrier board
> >>
> >> From: Frieder Schrempf <frieder.schrempf@...tron.de>
> >>
> >> This adds support for the Kontron Electronics OSM-S i.MX93 SoM
> and
> >> the matching baseboard BL i.MX93.
> >>
> >> The SoM hardware complies to the Open Standard Module (OSM)
> 1.1
> >> specification, size S
> >>
> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@...tron.de>
> >> ---
> >> arch/arm64/boot/dts/freescale/Makefile | 1 +
> >> .../dts/freescale/imx93-kontron-bl-osm-s.dts | 165 ++++++
> >> .../dts/freescale/imx93-kontron-osm-s.dtsi | 547
> >> ++++++++++++++++++
> >> 3 files changed, 713 insertions(+)
> >> create mode 100644 arch/arm64/boot/dts/freescale/imx93-
> kontron-
> >> bl-osm-s.dts
> >> create mode 100644 arch/arm64/boot/dts/freescale/imx93-
> kontron-
> >> osm-s.dtsi
> >>
> >> diff --git a/arch/arm64/boot/dts/freescale/Makefile
> >> b/arch/arm64/boot/dts/freescale/Makefile
> >> index f04c22b7de72e..c6e82dfe37576 100644
> >> --- a/arch/arm64/boot/dts/freescale/Makefile
> >> +++ b/arch/arm64/boot/dts/freescale/Makefile
> >> @@ -238,6 +238,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-
> >> tqma8xqp-mba8xx.dtb
> >> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> >> dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
> >> dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> >> +dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
> >> dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> >> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> >> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb diff
> -- git
> >> a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts
> >> b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts
> >> new file mode 100644
> >> index 0000000000000..2dfa2381f4691
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts
> >> @@ -0,0 +1,165 @@
> >> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> >> +/*
> >> + * Copyright (C) 2024 Kontron Electronics GmbH */
> >> +
> >> +/dts-v1/;
> >> +
> >> +#include "imx93-kontron-osm-s.dtsi"
> >> +
> >> +/ {
> >> + model = "Kontron BL i.MX93 OSM-S";
> >> + compatible = "kontron,imx93-bl-osm-s", "kontron,imx93-osm-
> >> s",
> >> +"fsl,imx93";
> >> +
> >> + aliases {
> >> + ethernet0 = &fec;
> >> + ethernet1 = &eqos;
> >> + };
> >> +
> >> + leds {
> >> + compatible = "gpio-leds";
> >> +
> >> + led1 {
> >> + label = "led1";
> >> + gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
> >> + linux,default-trigger = "heartbeat";
> >> + };
> >> + };
> >> +
> >> + pwm-beeper {
> >> + compatible = "pwm-beeper";
> >> + pwms = <&tpm6 1 5000 0>;
> >> + };
> >> +
> >> + reg_vcc_panel: regulator-vcc-panel {
> >> + compatible = "regulator-fixed";
> >> + enable-active-high;
> >> + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
> >
> > "enable-active-high" should be put under gpio property.
>
> Hm, alphabetically 'e' comes before 'g'. And I see a lot of occurences in
> the tree where the order is like this. So I'm not really convinced it
> should be the other way round.
I just take comments here:
https://lore.kernel.org/all/Zm+Mu33s2+8G579d@dragon/
Regards,
Peng.
>
> >
> >> + regulator-max-microvolt = <3300000>;
> >> + regulator-min-microvolt = <3300000>;
> >> + regulator-name = "VCC_PANEL";
> >> + };
> >> +};
> >> +
> >> +&lpspi8 {
> >> + status = "okay";
> >> + assigned-clocks = <&clk IMX93_CLK_LPSPI8>;
> >> + assigned-clock-parents = <&clk
> >> IMX93_CLK_SYS_PLL_PFD0_DIV2>;
> >> + assigned-clock-rates = <100000000>;
> >> +
> >> + eeram@0 {
> >> + compatible = "microchip,48l640";
> >> + reg = <0>;
> >> + spi-max-frequency = <20000000>;
> >> + };
> >> +};
> >> +
> >> +&eqos { /* Second ethernet (OSM-S ETH_B) */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_eqos_rgmii>;
> >> + phy-mode = "rgmii-id";
> >> + phy-handle = <ðphy1>;
> >> + status = "okay";
> >> +
> >> + mdio {
> >> + compatible = "snps,dwmac-mdio";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + ethphy1: ethernet-phy@1 {
> >> + compatible = "ethernet-phy-id4f51.e91b";
> >> + reg = <1>;
> >> + reset-assert-us = <10000>;
> >> + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> >> + };
> >> + };
> >> +};
> >> +
> >> +&fec { /* First ethernet (OSM-S ETH_A) */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_enet_rgmii>;
> >> + phy-connection-type = "rgmii-id";
> >> + phy-handle = <ðphy0>;
> >> + status = "okay";
> >> +
> >> + mdio {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + ethphy0: ethernet-phy@1 {
> >> + compatible = "ethernet-phy-id4f51.e91b";
> >> + reg = <1>;
> >> + reset-assert-us = <10000>;
> >> + reset-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
> >> + };
> >> + };
> >> +};
> >> +
> >> +&flexcan1 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&lpi2c2 {
> >> + status = "okay";
> >> +
> >> + gpio_expander_dio: gpio@20 {
> >> + compatible = "ti,tca6408";
> >> + reg = <0x20>;
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> + gpio-line-names = "DIO1_OUT","DIO1_IN",
> >> "DIO2_OUT","DIO2_IN",
> >> + "DIO3_OUT","DIO3_IN",
> >> "DIO4_OUT","DIO4_IN";
> >> + interrupt-parent = <&gpio4>;
> >> + interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
> >> + reset-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
> >> + };
> >> +};
> >> +
> >> +&lpuart1 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&lpuart7 {
> >> + uart-has-rtscts;
> >> + status = "okay";
> >> +};
> >> +
> >> +&lpuart6 {
> >> + linux,rs485-enabled-at-boot-time;
> >> + uart-has-rtscts;
> >> + status = "okay";
> >> +};
> >> +
> >> +&tpm6 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&usbotg1 {
> >> + disable-over-current;
> >> + dr_mode = "host";
> >> + status = "okay";
> >> +
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + usb1@1 {
> >> + compatible = "usb424,2514";
> >> + reg = <1>;
> >> + };
> >> +};
> >> +
> >> +&usbotg2 {
> >> + adp-disable;
> >> + hnp-disable;
> >> + srp-disable;
> >> +
> >> + disable-over-current;
> >> + dr_mode = "otg";
> >> + usb-role-switch;
> >> + status = "okay";
> >> +};
> >> +
> >> +&usdhc2 {
> >> + vmmc-supply = <®_vdd_3v3>;
> >> + status = "okay";
> >> +};
> >> diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi
> >> b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi
> >> new file mode 100644
> >> index 0000000000000..926c622d380ee
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi
> >> @@ -0,0 +1,547 @@
> >> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> >> +/*
> >> + * Copyright (C) 2024 Kontron Electronics GmbH */
> >> +
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >> +#include "imx93.dtsi"
> >> +
> >> +/ {
> >> + model = "Kontron OSM-S i.MX93";
> >> + compatible = "kontron,imx93-osm-s", "fsl,imx93";
> >> +
> >> + aliases {
> >> + rtc0 = &rv3028;
> >> + rtc1 = &bbnsm_rtc;
> >> + };
> >> +
> >> + memory@...00000 {
> >> + device_type = "memory";
> >> + reg = <0x0 0x40000000 0 0x80000000>;
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = &lpuart1;
> >> + };
> >> +
> >> + reg_usdhc2_vcc: regulator-usdhc2-vcc {
> >> + compatible = "regulator-fixed";
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
> >> + enable-active-high;
> >> + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
> >
> > "enable-active-high" put under "gpio".
> >
> >> + regulator-min-microvolt = <3300000>;
> >> + regulator-max-microvolt = <3300000>;
> >> + regulator-name = "VCC_SDIO_A";
> >> + };
> >> +
> >> + reg_vdd_carrier: regulator-vdd-carrier {
> >> + compatible = "regulator-fixed";
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
> >> + enable-active-high;
> >> + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
> >
> > Ditto.
> >
> >> + regulator-always-on;
> >> + regulator-boot-on;
> >> + regulator-name = "VDD_CARRIER";
> >> +
> >> + regulator-state-standby {
> >> + regulator-on-in-suspend;
> >> + };
> >> +
> >> + regulator-state-mem {
> >> + regulator-off-in-suspend;
> >> + };
> >> +
> >> + regulator-state-disk {
> >> + regulator-off-in-suspend;
> >> + };
> >> + };
> >> +};
> >> +
> >> +&lpspi1 { /* OSM-S SPI_A */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpspi1>;
> >> + cs-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; };
> >> +
> >> +&lpspi8 { /* OSM-S SPI_B */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpspi8>;
> >> + cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; };
> >> +
> >> +&flexcan1 { /* OSM-S CAN_A */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_flexcan1>;
> >> +};
> >> +
> >> +&flexcan2 { /* OSM-S CAN_B */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_flexcan2>;
> >> +};
> >> +
> >> +&gpio1 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_gpio1>;
> >> + gpio-line-names = "", "", "I2C_A_SCL", "I2C_A_SDA",
> >> + "UART_CON_RX", "UART_CON_TX",
> >> "UART_C_RX", "UART_C_TX",
> >> + "CAN_A_TX", "CAN_A_RX", "GPIO_A_0",
> >> "SPI_A_CS0",
> >> + "SPI_A_SDI", "SPI_A_SCK","SPI_A_SDO"; };
> >> +
> >> +&gpio2 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_gpio2>;
> >> + gpio-line-names = "I2C_B_SDA", "I2C_B_SCL", "GPIO_B_1",
> >> "GPIO_A_2",
> >> + "UART_B_TX", "UART_B_RX", "UART_B_RTS",
> >> "UART_B_CTS",
> >> + "UART_A_TX", "UART_A_RX", "UART_A_RTS",
> >> "UART_A_CTS",
> >> + "SPI_B_CS0", "SPI_B_SDI", "SPI_B_SDO",
> >> "SPI_B_SCK",
> >> + "I2S_BITCLK", "I2S_MCLK", "GPIO_A_1",
> >> "I2S_A_DATA_OUT",
> >> + "I2S_A_DATA_IN", "PWM_2", "GPIO_A_3",
> >> "PWM_1",
> >> + "PWM_0", "CAN_B_TX", "I2S_LRCLK",
> >> "CAN_B_RX", "GPIO_A_4",
> >> + "GPIO_A_5";
> >> +};
> >> +
> >> +&gpio3 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_gpio3>;
> >> + gpio-line-names = "SDIO_A_CD", "SDIO_A_CLK",
> >> "SDIO_A_CMD", "SDIO_A_D0",
> >> + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3",
> >> "SDIO_A_PWR_EN",
> >> + "", "", "", "",
> >> + "", "", "", "",
> >> + "", "", "", "",
> >> + "SDIO_B_CLK", "SDIO_B_CMD",
> >> "SDIO_B_D0", "SDIO_B_D1",
> >> + "SDIO_B_D2", "SDIO_B_D3", "GPIO_A_6",
> >> "GPIO_A_7"; };
> >> +
> >> +&gpio4 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_gpio4>;
> >> + gpio-line-names = "ETH_B_MDC", "ETH_B_MDIO",
> >> "ETH_B_TXD4", "ETH_B_TXD3",
> >> + "ETH_B_TXD2", "ETH_B_TXD1",
> >> "ETH_B_TX_EN", "ETH_B_TX_CLK",
> >> + "ETH_B_RX_CTL", "ETH_B_RX_CLK",
> >> "ETH_B_RXD0", "ETH_B_RXD1",
> >> + "ETH_B_RXD2", "ETH_B_RXD3", "ETH_MDC",
> >> "ETH_MDIO",
> >> + "ETH_A_TXD3", "ETH_A_TXD2",
> >> "ETH_A_TXD1", "ETH_A_TXD0",
> >> + "ETH_A_TX_EN", "ETH_A_TX_CLK",
> >> "ETH_A_RX_CTL", "ETH_A_RX_CLK",
> >> + "ETH_A_RXD0", "ETH_A_RXD1",
> >> "ETH_A_RXD2", "ETH_A_RXD3",
> >> + "GPIO_B_0", "CARRIER_PWR_EN";
> >> +};
> >> +
> >> +&lpi2c1 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpi2c1>;
> >> + status = "okay";
> >> +
> >> + pca9451: pmic@25 {
> >> + compatible = "nxp,pca9451a";
> >> + reg = <0x25>;
> >> + nxp,i2c-lt-enable;
> >> +
> >> + regulators {
> >> + reg_vdd_soc: BUCK1 { /* dual phase with
> >> BUCK3 */
> >> + regulator-name = "+0V8_VDD_SOC
> >> (BUCK1)";
> >> + regulator-min-microvolt = <650000>;
> >> + regulator-max-microvolt = <950000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + regulator-ramp-delay = <3125>;
> >> + };
> >> +
> >> + reg_vddq_ddr: BUCK2 {
> >> + regulator-name = "+0V6_VDDQ_DDR
> >> (BUCK2)";
> >> + regulator-min-microvolt = <600000>;
> >> + regulator-max-microvolt = <600000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + regulator-ramp-delay = <3125>;
> >> + };
> >> +
> >> + reg_vdd_3v3: BUCK4 {
> >> + regulator-name = "+3V3 (BUCK4)";
> >> + regulator-min-microvolt =
> >> <3300000>;
> >> + regulator-max-microvolt =
> >> <3300000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + reg_vdd_1v8: BUCK5 {
> >> + regulator-name = "+1V8 (BUCK5)";
> >> + regulator-min-microvolt =
> >> <1800000>;
> >> + regulator-max-microvolt =
> >> <1800000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + reg_nvcc_dram: BUCK6 {
> >> + regulator-name =
> >> "+1V1_NVCC_DRAM (BUCK6)";
> >> + regulator-min-microvolt =
> >> <1100000>;
> >> + regulator-max-microvolt =
> >> <1100000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + reg_nvcc_snvs: LDO1 {
> >> + regulator-name = "+1V8_NVCC_SNVS
> >> (LDO1)";
> >> + regulator-min-microvolt =
> >> <1800000>;
> >> + regulator-max-microvolt =
> >> <1800000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + reg_vdd_ana: LDO4 {
> >> + regulator-name = "+0V8_VDD_ANA
> >> (LDO4)";
> >> + regulator-min-microvolt = <800000>;
> >> + regulator-max-microvolt = <800000>;
> >> + regulator-boot-on;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + reg_nvcc_sd: LDO5 {
> >> + regulator-name = "NVCC_SD (LDO5)";
> >> + regulator-min-microvolt =
> >> <1800000>;
> >> + regulator-max-microvolt =
> >> <3300000>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + eeprom@50 {
> >> + compatible = "onnn,n24s64b", "atmel,24c64";
> >> + reg = <0x50>;
> >> + pagesize = <32>;
> >> + size = <8192>;
> >> + num-addresses = <1>;
> >> + };
> >> +
> >> + rv3028: rtc@52 {
> >> + compatible = "microcrystal,rv3028";
> >> + reg = <0x52>;
> >> + };
> >> +};
> >> +
> >> +&lpi2c2 { /* OSM-S I2C_A */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpi2c2>;
> >> +};
> >> +
> >> +&lpi2c3 { /* OSM-S I2C_B */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpi2c3>;
> >> +};
> >> +
> >> +&tpm3 { /* OSM-S PWM_0 */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_tpm3>;
> >> +};
> >> +
> >> +&tpm4 { /* OSM-S PWM_2 */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_tpm4>;
> >> +};
> >> +
> >> +&tpm6 { /* OSM-S PWM_1 */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_tpm6>;
> >> +};
> >> +
> >> +&lpuart1 { /* OSM-S UART_CON */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpuart1>;
> >> +};
> >> +
> >> +&lpuart2 { /* OSM-S UART_C */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpuart2>;
> >> +};
> >> +
> >> +&lpuart6 { /* OSM-S UART_B */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpuart6>;
> >> +};
> >> +
> >> +&lpuart7 { /* OSM-S UART_A */
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_lpuart7>;
> >> +};
> >> +
> >> +&usdhc1 { /* eMMC */
> >> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> >> + pinctrl-0 = <&pinctrl_usdhc1>;
> >> + pinctrl-1 = <&pinctrl_usdhc1>;
> >> + pinctrl-2 = <&pinctrl_usdhc1>;
> >
> > Same pad settings?
>
> I will update this to use adjusted settings for the different speed modes.
>
> >
> >> + vmmc-supply = <®_vdd_3v3>;
> >> + vqmmc-supply = <®_vdd_1v8>;
> >> + bus-width = <8>;
> >> + non-removable;
> >> + status = "okay";
> >> +};
> >> +
> >> +&usdhc2 { /* OSM-S SDIO_A */
> >> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> >> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> >> + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> >> + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> >
> > Ditto.
>
> I will change this, too.
>
> >
> >> + vmmc-supply = <®_usdhc2_vcc>;
> >> + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; };
> >> +
> >> +&usdhc3 { /* OSM-S SDIO_B */
> >> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> >> + pinctrl-0 = <&pinctrl_usdhc3>;
> >> + pinctrl-1 = <&pinctrl_usdhc3>;
> >> + pinctrl-2 = <&pinctrl_usdhc3>;
> >
> > Ditto.
>
> I will change this, too.
>
> Thanks
> Frieder
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