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Message-ID: <CAAhSdy2ATNkx4cpMLpVrBUbxSG+WVbOFpMA8LQcMAE2jGSs4ng@mail.gmail.com>
Date: Tue, 6 Aug 2024 20:55:34 +0530
From: Anup Patel <anup@...infault.org>
To: Sunil V L <sunilvl@...tanamicro.com>
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-riscv@...ts.infradead.org, linux-pci@...r.kernel.org,
Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
"Rafael J . Wysocki" <rafael@...nel.org>, Len Brown <lenb@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Thomas Gleixner <tglx@...utronix.de>, Samuel Holland <samuel.holland@...ive.com>,
Robert Moore <robert.moore@...el.com>, Conor Dooley <conor.dooley@...rochip.com>,
Andrew Jones <ajones@...tanamicro.com>, Haibo Xu <haibo1.xu@...el.com>,
Atish Kumar Patra <atishp@...osinc.com>, Drew Fustini <dfustini@...storrent.com>
Subject: Re: [PATCH v7 14/17] irqchip/riscv-imsic-state: Create separate
function for DT
On Mon, Jul 29, 2024 at 7:54 PM Sunil V L <sunilvl@...tanamicro.com> wrote:
>
> While populating IMSIC global structure, many fields are initialized
> using DT properties. Make the code which uses DT properties as separate
> function so that it is easier to add ACPI support later. No
> functionality added/changed.
>
> Suggested-by: Thomas Gleixner <tglx@...utronix.de>
> Signed-off-by: Sunil V L <sunilvl@...tanamicro.com>
LGTM.
Reviewed-by: Anup Patel <anup@...infault.org>
Regards,
Anup
> ---
> drivers/irqchip/irq-riscv-imsic-state.c | 97 ++++++++++++++-----------
> 1 file changed, 55 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c
> index 5479f872e62b..f9e70832863a 100644
> --- a/drivers/irqchip/irq-riscv-imsic-state.c
> +++ b/drivers/irqchip/irq-riscv-imsic-state.c
> @@ -510,6 +510,60 @@ static int __init imsic_matrix_init(void)
> return 0;
> }
>
> +static int __init imsic_populate_global_dt(struct fwnode_handle *fwnode,
> + struct imsic_global_config *global,
> + u32 *nr_parent_irqs)
> +{
> + int rc;
> +
> + /* Find number of guest index bits in MSI address */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
> + &global->guest_index_bits);
> + if (rc)
> + global->guest_index_bits = 0;
> +
> + /* Find number of HART index bits */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
> + &global->hart_index_bits);
> + if (rc) {
> + /* Assume default value */
> + global->hart_index_bits = __fls(*nr_parent_irqs);
> + if (BIT(global->hart_index_bits) < *nr_parent_irqs)
> + global->hart_index_bits++;
> + }
> +
> + /* Find number of group index bits */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
> + &global->group_index_bits);
> + if (rc)
> + global->group_index_bits = 0;
> +
> + /*
> + * Find first bit position of group index.
> + * If not specified assumed the default APLIC-IMSIC configuration.
> + */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
> + &global->group_index_shift);
> + if (rc)
> + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
> +
> + /* Find number of interrupt identities */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
> + &global->nr_ids);
> + if (rc) {
> + pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
> + return rc;
> + }
> +
> + /* Find number of guest interrupt identities */
> + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
> + &global->nr_guest_ids);
> + if (rc)
> + global->nr_guest_ids = global->nr_ids;
> +
> + return 0;
> +}
> +
> static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
> u32 index, unsigned long *hartid)
> {
> @@ -578,50 +632,9 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
> return -EINVAL;
> }
>
> - /* Find number of guest index bits in MSI address */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
> - &global->guest_index_bits);
> + rc = imsic_populate_global_dt(fwnode, global, nr_parent_irqs);
> if (rc)
> - global->guest_index_bits = 0;
> -
> - /* Find number of HART index bits */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
> - &global->hart_index_bits);
> - if (rc) {
> - /* Assume default value */
> - global->hart_index_bits = __fls(*nr_parent_irqs);
> - if (BIT(global->hart_index_bits) < *nr_parent_irqs)
> - global->hart_index_bits++;
> - }
> -
> - /* Find number of group index bits */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
> - &global->group_index_bits);
> - if (rc)
> - global->group_index_bits = 0;
> -
> - /*
> - * Find first bit position of group index.
> - * If not specified assumed the default APLIC-IMSIC configuration.
> - */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
> - &global->group_index_shift);
> - if (rc)
> - global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
> -
> - /* Find number of interrupt identities */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
> - &global->nr_ids);
> - if (rc) {
> - pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
> return rc;
> - }
> -
> - /* Find number of guest interrupt identities */
> - rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
> - &global->nr_guest_ids);
> - if (rc)
> - global->nr_guest_ids = global->nr_ids;
>
> /* Sanity check guest index bits */
> i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;
> --
> 2.43.0
>
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