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Message-ID: <ZrOUGLJPYC/K4MlP@lizhi-Precision-Tower-5810>
Date: Wed, 7 Aug 2024 11:34:48 -0400
From: Frank Li <Frank.li@....com>
To: Francesco Dolcini <francesco@...cini.it>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Francesco Dolcini <francesco.dolcini@...adex.com>,
devicetree@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 4/4] arm64: dts: imx8-ss-conn: add PPS channel to the
FEC nodes
On Wed, Aug 07, 2024 at 04:43:49PM +0200, Francesco Dolcini wrote:
> From: Francesco Dolcini <francesco.dolcini@...adex.com>
>
> On i.MX8 the FEC PPS channel is routed to the instance 1, not to the
> default 0.
According to my understand, it should be board level configuration. FEC
support output pps to any one. choose which one by board design.
Frank
>
> Signed-off-by: Francesco Dolcini <francesco.dolcini@...adex.com>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> index a4a10ce03bfe..a9fd47041e3a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> @@ -121,6 +121,7 @@ fec1: ethernet@...40000 {
> assigned-clock-rates = <250000000>, <125000000>;
> fsl,num-tx-queues = <3>;
> fsl,num-rx-queues = <3>;
> + fsl,pps-channel = <1>;
> power-domains = <&pd IMX_SC_R_ENET_0>;
> status = "disabled";
> };
> @@ -141,6 +142,7 @@ fec2: ethernet@...50000 {
> assigned-clock-rates = <250000000>, <125000000>;
> fsl,num-tx-queues = <3>;
> fsl,num-rx-queues = <3>;
> + fsl,pps-channel = <1>;
> power-domains = <&pd IMX_SC_R_ENET_1>;
> status = "disabled";
> };
> --
> 2.39.2
>
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