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Message-ID: <20240807211342.1660-1-logan.bristol@utexas.edu>
Date: Wed, 7 Aug 2024 16:13:42 -0500
From: Logan Bristol <logan.bristol@...xas.edu>
To: Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Vignesh Raghavendra <vigneshr@...com>,
Nishanth Menon <nm@...com>
Cc: Josua Mayer <josua@...id-run.com>,
Matt McKee <mmckee@...tec.com>,
Wadim Egorov <w.egorov@...tec.de>,
linux@...tq-group.com,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Logan Bristol <logan.bristol@...xas.edu>
Subject: [PATCH] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
External interfaces should be disabled at the SoC DTSI level, since
the node is incomplete. The node should then be enabled in the board DTS.
Disable ethernet switch and ports in SoC DTSI and enable them in the board
DTS.
Reflect this change in SoM DTSIs by removing ethernet port disable.
Signed-off-by: Logan Bristol <logan.bristol@...xas.edu>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 4 ----
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts | 8 ++++++++
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 8 ++++++++
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 4 ----
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
8 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index f8370dd03350..69c5af58b727 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -677,6 +677,7 @@ cpsw3g: ethernet@...0000 {
assigned-clock-parents = <&k3_clks 13 9>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
dmas = <&main_pktdma 0xC500 15>,
<&main_pktdma 0xC501 15>,
@@ -701,6 +702,7 @@ cpsw_port1: port@1 {
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&main_conf 0x200>;
+ status = "disabled";
};
cpsw_port2: port@2 {
@@ -709,6 +711,7 @@ cpsw_port2: port@2 {
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
+ status = "disabled";
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index ea7c58fb67e2..ec269742d060 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -210,10 +210,6 @@ &cpsw_port1 {
phy-handle = <&cpsw3g_phy1>;
};
-&cpsw_port2 {
- status = "disabled";
-};
-
&mailbox0_cluster2 {
status = "okay";
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 6bb1ad2e56ec..82da21bd9aea 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -616,17 +616,20 @@ &cpsw3g {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
+ status = "okay";
};
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
+ status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
+ status = "okay";
};
&cpsw3g_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts
index 5b5e9eeec5ac..90ffc426cae1 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-hummingboard-t.dts
@@ -89,6 +89,14 @@ serdes_mux: mux-controller {
};
};
+&cpsw3g {
+ status = "okay";
+};
+
+&cpsw_port1 {
+ status ="okay";
+};
+
&main_gpio0 {
m2-reset-hog {
gpio-hog;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index 30729b49dd69..d43270fad441 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -198,6 +198,14 @@ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
};
};
+&cpsw3g {
+ status = "okay";
+};
+
+&cpsw_port1 {
+ status = "okay";
+};
+
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 44ecbcf1c844..86369525259c 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -527,16 +527,19 @@ &usb0 {
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
+ status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
+ status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
+ status = "okay";
};
&cpsw3g_mdio {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
index c19d0b8bbf0f..995e2703030b 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
@@ -212,10 +212,6 @@ &cpsw_port1 {
phy-handle = <ðernet_phy0>;
};
-&cpsw_port2 {
- status = "disabled";
-};
-
&icssg1_mdio {
pinctrl-names = "default";
pinctrl-0 = <&pru1_mdio0_default_pins>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index c40ad67cee01..8d7a0283c391 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -119,15 +119,13 @@ reg_sd: regulator-sd {
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_pins>;
+ status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- status = "disabled";
+ status = "okay";
};
&cpsw3g_mdio {
--
2.34.1
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