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Message-ID: <20240807051341.1616925-5-Vijendar.Mukunda@amd.com>
Date: Wed, 7 Aug 2024 10:43:17 +0530
From: Vijendar Mukunda <Vijendar.Mukunda@....com>
To: <broonie@...nel.org>
CC: <alsa-devel@...a-project.org>, <Basavaraj.Hiregoudar@....com>,
<Sunil-kumar.Dommati@....com>, <venkataprasad.potturu@....com>, "Vijendar
Mukunda" <Vijendar.Mukunda@....com>, Ranjani Sridharan
<ranjani.sridharan@...ux.intel.com>, Pierre-Louis Bossart
<pierre-louis.bossart@...ux.intel.com>, Liam Girdwood <lgirdwood@...il.com>,
Peter Ujfalusi <peter.ujfalusi@...ux.intel.com>, Bard Liao
<yung-chuan.liao@...ux.intel.com>, Daniel Baluta <daniel.baluta@....com>,
"Kai Vehmanen" <kai.vehmanen@...ux.intel.com>, Jaroslav Kysela
<perex@...ex.cz>, Takashi Iwai <tiwai@...e.com>, Cristian Ciocaltea
<cristian.ciocaltea@...labora.com>, "moderated list:SOUND - SOUND OPEN
FIRMWARE (SOF) DRIVERS" <sound-open-firmware@...a-project.org>, "open
list:SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEM..."
<linux-sound@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>
Subject: [PATCH 5/8] ASoC: SOF: amd: update conditional check for cache register update
Instead of desc->rev, use acp pci revision id(pci_rev) for cache register
conditional check.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@....com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
---
sound/soc/sof/amd/acp-loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/sof/amd/acp-loader.c b/sound/soc/sof/amd/acp-loader.c
index 2d5e58846499..19f10dd77e4b 100644
--- a/sound/soc/sof/amd/acp-loader.c
+++ b/sound/soc/sof/amd/acp-loader.c
@@ -219,7 +219,7 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev)
dev_err(sdev->dev, "acp dma transfer status: %d\n", ret);
}
- if (desc->rev > 3) {
+ if (adata->pci_rev > ACP_RN_PCI_ID) {
/* Cache Window enable */
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_OFFSET0, desc->sram_pte_offset);
snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_SIZE0, SRAM1_SIZE | BIT(31));
--
2.34.1
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