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Message-ID:
<ZQ0PR01MB12539F35A27177E1CCAC43D89FB82@ZQ0PR01MB1253.CHNPR01.prod.partner.outlook.cn>
Date: Wed, 7 Aug 2024 03:41:15 +0000
From: William Qiu <william.qiu@...rfivetech.com>
To: Uwe Kleine-König <u.kleine-koenig@...libre.com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>, Hal Feng
<hal.feng@...rfivetech.com>, Philipp Zabel <p.zabel@...gutronix.de>
Subject: RE: [PATCH v13] pwm: opencores: Add PWM driver support
> -----Original Message-----
> From: Uwe Kleine-König <u.kleine-koenig@...libre.com>
> Sent: 2024年8月7日 1:19
> To: William Qiu <william.qiu@...rfivetech.com>
> Cc: linux-kernel@...r.kernel.org; linux-pwm@...r.kernel.org; Hal Feng
> <hal.feng@...rfivetech.com>; Philipp Zabel <p.zabel@...gutronix.de>
> Subject: Re: [PATCH v13] pwm: opencores: Add PWM driver support
>
> Hello William,
>
> On Tue, Jul 02, 2024 at 04:38:48PM +0800, William Qiu wrote:
> > Add driver for OpenCores PWM Controller. And add compatibility code
> > which based on StarFive SoC.
> >
> > Co-developed-by: Hal Feng <hal.feng@...rfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> > Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
> > ---
> > MAINTAINERS | 7 ++
> > drivers/pwm/Kconfig | 12 ++
> > drivers/pwm/Makefile | 1 +
> > drivers/pwm/pwm-ocores.c | 239
> > +++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 259 insertions(+)
> > create mode 100644 drivers/pwm/pwm-ocores.c [...] diff --git
> > a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode
> > 100644 index 000000000000..c8f08aa14e44
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-ocores.c
> > @@ -0,0 +1,239 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * OpenCores PWM Driver
> > + *
> > + * https://opencores.org/projects/ptc
> > + *
> > + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
> > + *
> > + * Limitations:
> > + * - The hardware only supports inverted polarity.
> > + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock
> frequency) ns.
> > + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb
> clock frequency) ns.
>
> Nitpick: s/ ns//
>
Will update.
> > + * - The hardware is set to a low level immediately when disabledThe
> hardware is set to
> > + * a low level immediately when disabled.
>
> This sentence is duplicated somehow. Maybe also: s/hardware/output/ ?
>
Will update.
> > + * - The hardware will have a conversion cycle when reconfiguring.
>
> I don't understand that.
> .
For example, after the PWM duty cycle is changed from 50% to 80%,
it is not a direct change, but there is a conversion period. The waveform
during the conversion period will vary depending on whether it is high or
low when reconfigured.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pwm.h>
> > +#include <linux/reset.h>
> > +#include <linux/slab.h>
> > +
> > +/* OpenCores Register offsets */
> > +#define REG_OCPWM_CNTR 0x0
> > +#define REG_OCPWM_HRC 0x4
> > +#define REG_OCPWM_LRC 0x8
> > +#define REG_OCPWM_CTRL 0xC
> > +
> > +/* OCPWM_CTRL register bits*/
> > +#define REG_OCPWM_CNTR_EN BIT(0)
> > +#define REG_OCPWM_CNTR_ECLK BIT(1)
> > +#define REG_OCPWM_CNTR_NEC BIT(2)
> > +#define REG_OCPWM_CNTR_OE BIT(3)
> > +#define REG_OCPWM_CNTR_SIGNLE BIT(4)
> > +#define REG_OCPWM_CNTR_INTE BIT(5)
> > +#define REG_OCPWM_CNTR_INT BIT(6)
> > +#define REG_OCPWM_CNTR_RST BIT(7)
> > +#define REG_OCPWM_CNTR_CAPTE BIT(8)
> > +
> > +struct ocores_pwm_device {
> > + const struct ocores_pwm_data *data;
>
> I admit I didn't try to compile this, but I wonder if this doesn't result in a
> compiler warning given that struct ocores_pwm_data is only defined below.
>
Will update.
> > + void __iomem *regs;
> > + u32 clk_rate; /* PWM APB clock frequency */ };
> > +
> > +struct ocores_pwm_data {
> > + void __iomem *(*get_ch_base)(void __iomem *base, unsigned int
> > +channel); };
> > [...]
> > +static int ocores_pwm_apply(struct pwm_chip *chip,
> > + struct pwm_device *pwm,
> > + const struct pwm_state *state) {
> > + struct ocores_pwm_device *ddata = chip_to_ocores(chip);
> > + u32 ctrl_data = 0;
> > + u64 period_data, duty_data;
> > +
> > + if (state->polarity != PWM_POLARITY_INVERSED)
> > + return -EINVAL;
> > +
> > + period_data = mul_u64_u32_div(state->period, ddata->clk_rate,
> NSEC_PER_SEC);
> > + if (!period_data)
> > + return -EINVAL;
> > +
> > + if (period_data > U32_MAX)
> > + period_data = U32_MAX;
> > +
> > + ocores_pwm_writel(ddata, pwm->hwpwm, 0x8, (u32)period_data);
>
> s/0x8/REG_OCPWM_LRC/ ?
>
Will update.
> That cast can be dropped.
>
> > + duty_data = mul_u64_u32_div(state->duty_cycle, ddata->clk_rate,
> NSEC_PER_SEC);
> > + if (duty_data <= U32_MAX)
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_HRC,
> (u32)duty_data);
> > + else if (duty_data > U32_MAX)
> > + duty_data = U32_MAX;
> > + else
> > + return -EINVAL;
>
> That looks wrong. If duty_data > U32_MAX you assign duty_data but don't
> reuse this variable later.
>
Will update.
> > +
> > + ctrl_data = ocores_pwm_readl(ddata, pwm->hwpwm,
> REG_OCPWM_CTRL);
> > + if (state->enabled)
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_CTRL,
> > + ctrl_data | REG_OCPWM_CNTR_EN |
> REG_OCPWM_CNTR_OE);
> > + else
> > + ocores_pwm_writel(ddata, pwm->hwpwm, REG_OCPWM_CTRL,
> > + ctrl_data & ~(REG_OCPWM_CNTR_EN |
> REG_OCPWM_CNTR_OE));
> > +
> > + return 0;
> > +}
> > [...]
> > +static int ocores_pwm_probe(struct platform_device *pdev) {
> > + const struct of_device_id *id;
> > + struct device *dev = &pdev->dev;
> > + struct ocores_pwm_device *ddata;
> > + struct pwm_chip *chip;
> > + struct clk *clk;
> > + struct reset_control *rst;
> > + int ret;
> > +
> > + id = of_match_device(ocores_pwm_of_match, dev);
> > + if (!id)
> > + return -EINVAL;
> > +
> > + chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*ddata));
> > + if (IS_ERR(chip))
> > + return -ENOMEM;
> > +
> > + ddata = chip_to_ocores(chip);
> > + ddata->data = id->data;
> > + chip->ops = &ocores_pwm_ops;
> > +
> > + ddata->regs = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(ddata->regs))
> > + return dev_err_probe(dev, PTR_ERR(ddata->regs),
> > + "Unable to map IO resources\n");
> > +
> > + clk = devm_clk_get_enabled(dev, NULL);
> > + if (IS_ERR(clk))
> > + return dev_err_probe(dev, PTR_ERR(clk),
> > + "Unable to get pwm's clock\n");
> > +
> > + ret = devm_clk_rate_exclusive_get(dev, clk);
> > + if (ret)
> > + return ret;
> > +
> > + rst = devm_reset_control_get_optional_exclusive(dev, NULL);
> > + if (IS_ERR(rst))
> > + return dev_err_probe(dev, PTR_ERR(rst),
> > + "Unable to get pwm's reset\n");
> > +
> > + reset_control_deassert(rst);
>
> I think you want to check the return value of reset_control_deassert().
>
Will add.
> > + ret = devm_add_action_or_reset(dev, ocores_pwm_reset_control_assert,
> rst);
> > + if (ret)
> > + return ret;
> > +
> > + ddata->clk_rate = clk_get_rate(clk);
> > + if (ddata->clk_rate > NSEC_PER_SEC)
> > + return dev_err_probe(dev, ddata->clk_rate,
> > + "Unable to get clock's rate\n");
>
> Best regards
> Uwe
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