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Message-ID: <3bce26bc327b4d1c63bf0ef32caae854893969a0.camel@ew.tq-group.com>
Date: Wed, 07 Aug 2024 14:02:34 +0200
From: Matthias Schiffer <matthias.schiffer@...tq-group.com>
To: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>, Tero
Kristo <kristo@...nel.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux@...tq-group.com
Subject: Re: [PATCH v2] arm64: dts: ti: k3-am642-tqma64xxl-mbax4xxl: add PRU
Ethernet support
On Mon, 2024-06-24 at 15:42 +0200, Matthias Schiffer wrote:
> Add PRU Ethernet controller and PHY nodes, as it was previously done for
> the AM64x EVM Device Trees.
>
> Signed-off-by: Matthias Schiffer <matthias.schiffer@...tq-group.com>
> ---
>
> v2:
> - Dropped binding change patch
> - Moved prueth device node to DTS toplevel, matching the AM64x EVM
> - Update firmware filenames to match EVM
Hi, are there any issues remaining with this patch?
Best,
Matthias
>
> .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 98 +++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> index 1f4dc5ad1696a..204f5e48a9c63 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> @@ -24,6 +24,8 @@ / {
>
> aliases {
> ethernet0 = &cpsw_port1;
> + ethernet1 = &icssg1_emac0;
> + ethernet2 = &icssg1_emac1;
> i2c1 = &mcu_i2c0;
> mmc1 = &sdhci1;
> serial0 = &mcu_uart0;
> @@ -71,6 +73,66 @@ led-1 {
> };
> };
>
> + icssg1_eth: icssg1-eth {
> + compatible = "ti,am642-icssg-prueth";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>;
> + interrupt-parent = <&icssg1_intc>;
> + interrupts = <24 0 2>, <25 1 3>;
> + interrupt-names = "tx_ts0", "tx_ts1";
> + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
> + <&main_pktdma 0xc201 15>, /* egress slice 0 */
> + <&main_pktdma 0xc202 15>, /* egress slice 0 */
> + <&main_pktdma 0xc203 15>, /* egress slice 0 */
> + <&main_pktdma 0xc204 15>, /* egress slice 1 */
> + <&main_pktdma 0xc205 15>, /* egress slice 1 */
> + <&main_pktdma 0xc206 15>, /* egress slice 1 */
> + <&main_pktdma 0xc207 15>, /* egress slice 1 */
> + <&main_pktdma 0x4200 15>, /* ingress slice 0 */
> + <&main_pktdma 0x4201 15>; /* ingress slice 1 */
> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
> + "tx1-0", "tx1-1", "tx1-2", "tx1-3",
> + "rx0", "rx1";
> + sram = <&oc_sram>;
> + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
> + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
> + ti,pruss-gp-mux-sel = <2>, /* MII mode */
> + <2>,
> + <2>,
> + <2>, /* MII mode */
> + <2>,
> + <2>;
> + ti,mii-g-rt = <&icssg1_mii_g_rt>;
> + ti,mii-rt = <&icssg1_mii_rt>;
> + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icssg1_emac0: port@0 {
> + reg = <0>;
> + phy-handle = <&icssg1_phy0c>;
> + phy-mode = "rgmii-id";
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> +
> + icssg1_emac1: port@1 {
> + reg = <1>;
> + phy-handle = <&icssg1_phy03>;
> + phy-mode = "rgmii-id";
> + /* Filled in by bootloader */
> + local-mac-address = [00 00 00 00 00 00];
> + };
> + };
> + };
> +
> fan0: pwm-fan {
> compatible = "pwm-fan";
> pinctrl-names = "default";
> @@ -154,6 +216,42 @@ &epwm5 {
> status = "okay";
> };
>
> +&icssg1_mdio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pru_icssg1_mdio_pins>;
> + status = "okay";
> +
> + /* phy-mode is fixed up to rgmii-rxid by prueth driver to account for
> + * the SoC integration, so the only rx-internal-delay and no
> + * tx-internal-delay is set for the PHYs.
> + */
> +
> + icssg1_phy03: ethernet-phy@3 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x3>;
> + reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <1000>;
> + reset-deassert-us = <1000>;
> + ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + };
> +
> + icssg1_phy0c: ethernet-phy@c {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0xc>;
> + reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <1000>;
> + reset-deassert-us = <1000>;
> + ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + };
> +};
> +
> +
> &main_gpio0 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_gpio0_digital_pins>,
--
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