linux-kernel - Re: [PATCH] x86/fpu: Avoid writing LBR bit to IA32

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Message-ID: <87plqhucnv.ffs@tglx>
Date: Fri, 09 Aug 2024 14:02:44 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Mitchell Levy via B4 Relay <devnull+levymitchell0.gmail.com@...nel.org>,
 Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, Dave
 Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org, "H. Peter Anvin"
 <hpa@...or.com>
Cc: stable@...r.kernel.org, Borislav Petkov <bp@...e.de>,
 linux-kernel@...r.kernel.org, Mitchell Levy <levymitchell0@...il.com>
Subject: Re: [PATCH] x86/fpu: Avoid writing LBR bit to IA32_XSS unless
 supported

On Fri, Aug 09 2024 at 11:52, Thomas Gleixner wrote:
>>  static inline u64 xfeatures_mask_independent(void)
>>  {
>> -	if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
>> +	if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) ||
>> +	    (fpu_kernel_cfg.max_features & XFEATURE_MASK_LBR) != XFEATURE_MASK_LBR)
>
> This is wrong because fpu_kernel_cfg.max_features never contains
> XFEATURE_MASK_LBR. It only contains the bits which are managed by the
> FPU subsystem.

You want something like the uncompiled below.

The LBR bit should be probably cleared when the CPU feature is not there
at some point in the boot process to avoid the whole is enabled and
masking business, but that's an orthogonal issue.

Thanks,

        tglx
---
 arch/x86/include/asm/fpu/types.h |    7 +++++++
 arch/x86/kernel/fpu/xstate.c     |    2 ++
 arch/x86/kernel/fpu/xstate.h     |    4 ++--
 3 files changed, 11 insertions(+), 2 deletions(-)

--- a/arch/x86/include/asm/fpu/types.h
+++ b/arch/x86/include/asm/fpu/types.h
@@ -591,6 +591,13 @@ struct fpu_state_config {
 	 * even without XSAVE support, i.e. legacy features FP + SSE
 	 */
 	u64 legacy_features;
+	/*
+	 * @independent_features:
+	 *
+	 * Features which are supported by XSAVES but not managed
+	 * by the FPU core, e.g. LBR
+	 */
+	u64 independent_features;
 };
 
 /* FPU state configuration information */
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -788,6 +788,8 @@ void __init fpu__init_system_xstate(unsi
 		goto out_disable;
 	}
 
+	fpu_kernel_cfg.independent_features = fpu_kernel_cfg.max_features &
+					      XFEATURE_MASK_INDEPENDENT;
 	/*
 	 * Clear XSAVE features that are disabled in the normal CPUID.
 	 */
--- a/arch/x86/kernel/fpu/xstate.h
+++ b/arch/x86/kernel/fpu/xstate.h
@@ -62,9 +62,9 @@ static inline u64 xfeatures_mask_supervi
 static inline u64 xfeatures_mask_independent(void)
 {
 	if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
-		return XFEATURE_MASK_INDEPENDENT & ~XFEATURE_MASK_LBR;
+		return fpu_kernel_cfg.independent_features & ~XFEATURE_MASK_LBR;
 
-	return XFEATURE_MASK_INDEPENDENT;
+	return fpu_kernel_cfg.independent_features;
 }
 
 /* XSAVE/XRSTOR wrapper functions */