linux-kernel - [PATCH v2 0/7] Add PCIe Root Port support for Agilex family of chips

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Message-Id: <20240809151213.94533-1-matthew.gerlach@linux.intel.com>
Date: Fri,  9 Aug 2024 10:12:06 -0500
From: matthew.gerlach@...ux.intel.com
To: lpieralisi@...nel.org,
	kw@...ux.com,
	robh@...nel.org,
	bhelgaas@...gle.com,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	dinguyen@...nel.org,
	joyce.ooi@...el.com,
	linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: [PATCH v2 0/7] Add PCIe Root Port support for Agilex family of chips

From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>

This patch set adds PCIe Root Port support for the Agilex family of FPGA chips.
Patches 1 and 2 have been reviewed previously and individually on the mailing
list and are included here with their revision history and Reviewed-by: tags
for convenience and completeness.

Patch 1: 
  Convert text device tree binding for Altera Root Port PCIe controller to YAML.
  No change from previous submission.

Patch 2:
  Convert text device tree binding for Altera PCIe MSI controller to YAML.
  No change from previous submission.

Patch 3:
  Add new compatible strings for the three variants of the Agilex PCIe controller IP.
  Added Reviewed-by: tag.

Patch 4:
  Add a label to the soc@0 device tree node to be used by patch 5.
  No change from previous submission.

Patch 5:
  Add base dtsi for PCIe Root Port support of the Agilex family of chips.
  Rename node name to fix device tree schema check error.

Patch 6:
  Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit.
  No change from previous submission.

Patch 7:
  Update Altera PCIe controller driver to support the Agilex family of chips.
  Address feedback from Bjorn Helgaas <helgaas@...nel.org>.

D M, Sharath Kumar (1):
  PCI: altera: Add Agilex support

Matthew Gerlach (6):
  dt-bindings: PCI: altera: Convert to YAML
  dt-bindings: PCI: altera: msi: Convert to YAML
  dt-bindings: PCI: altera: Add binding for Agilex
  arm64: dts: agilex: add soc0 label
  arm64: dts: agilex: add dtsi for PCIe Root Port
  arm64: dts: agilex: add dts enabling PCIe Root Port

 .../bindings/pci/altera-pcie-msi.txt          |  27 --
 .../devicetree/bindings/pci/altera-pcie.txt   |  50 ----
 .../bindings/pci/altr,msi-controller.yaml     |  65 +++++
 .../bindings/pci/altr,pcie-root-port.yaml     | 123 +++++++++
 MAINTAINERS                                   |   4 +-
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |   2 +-
 .../socfpga_agilex7f_socdk_pcie_root_port.dts |  16 ++
 .../intel/socfpga_agilex_pcie_root_port.dtsi  |  55 ++++
 drivers/pci/controller/pcie-altera.c          | 246 +++++++++++++++++-
 10 files changed, 500 insertions(+), 89 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altr,msi-controller.yaml
 create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi

-- 
2.34.1