linux-kernel - [PATCH 0/2] RISC-V: Add Zicclsm extension support

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Message-ID: <20240809162240.1842373-1-jesse@rivosinc.com>
Date: Fri,  9 Aug 2024 12:22:38 -0400
From: Jesse Taube <jesse@...osinc.com>
To: linux-riscv@...ts.infradead.org
Cc: Jonathan Corbet <corbet@....net>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Conor Dooley <conor@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Clément Léger <cleger@...osinc.com>,
	Evan Green <evan@...osinc.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Jesse Taube <jesse@...osinc.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Xiao Wang <xiao.w.wang@...el.com>,
	Andy Chiu <andy.chiu@...ive.com>,
	Eric Biggers <ebiggers@...gle.com>,
	Greentime Hu <greentime.hu@...ive.com>,
	Björn Töpel <bjorn@...osinc.com>,
	Heiko Stuebner <heiko@...ech.de>,
	Costa Shulyupin <costa.shul@...hat.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Baoquan He <bhe@...hat.com>,
	Anup Patel <apatel@...tanamicro.com>,
	Zong Li <zong.li@...ive.com>,
	Sami Tolvanen <samitolvanen@...gle.com>,
	Ben Dooks <ben.dooks@...ethink.co.uk>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	"Gustavo A. R. Silva" <gustavoars@...nel.org>,
	Erick Archer <erick.archer@....com>,
	Joel Granados <j.granados@...sung.com>,
	linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org
Subject: [PATCH 0/2] RISC-V: Add Zicclsm extension support

This set is the first two commits of
RISC-V: Detect and report speed of unaligned vector accesses [1]
rebased onto palmer/for-next.

The rational for adding Zicclsm was related to detecting unaligned
vector accesses though this reasoning is gone.

I don't see why Zicclsm shouldn't be added which is why
I'm sending this set.

[1] https://lore.kernel.org/all/20240726163719.1667923-1-jesse@rivosinc.com/

Jesse Taube (2):
  RISC-V: Add Zicclsm to cpufeature and hwprobe
  dt-bindings: riscv: Add Zicclsm ISA extension description.

 Documentation/arch/riscv/hwprobe.rst                    | 5 +++++
 Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
 arch/riscv/include/asm/hwcap.h                          | 1 +
 arch/riscv/include/uapi/asm/hwprobe.h                   | 1 +
 arch/riscv/kernel/cpufeature.c                          | 1 +
 arch/riscv/kernel/sys_hwprobe.c                         | 1 +
 6 files changed, 16 insertions(+)
---
base-commit: 2d1f51d8a4b0c3fc0b2b79d4e5b95a6813500092

-- 
2.45.2