linux-kernel - [tip: irq/urgent] irqchip/riscv-aplic: Retrigger MSI interrupt on source configuration

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Message-ID: <172327951735.2215.9481646283292037219.tip-bot2@tip-bot2>
Date: Sat, 10 Aug 2024 08:45:17 -0000
From: "tip-bot2 for Yong-Xuan Wang" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: "Yong-Xuan Wang" <yongxuan.wang@...ive.com>,
 Thomas Gleixner <tglx@...utronix.de>, Vincent Chen <vincent.chen@...ive.com>,
 Anup Patel <anup@...infault.org>, stable@...r.kernel.org, x86@...nel.org,
 linux-kernel@...r.kernel.org, maz@...nel.org
Subject: [tip: irq/urgent] irqchip/riscv-aplic: Retrigger MSI interrupt on
 source configuration

The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     03f9885c60adf73488fe32aab628ee3d4a39598e
Gitweb:        https://git.kernel.org/tip/03f9885c60adf73488fe32aab628ee3d4a39598e
Author:        Yong-Xuan Wang <yongxuan.wang@...ive.com>
AuthorDate:    Fri, 09 Aug 2024 15:10:47 +08:00
Committer:     Thomas Gleixner <tglx@...utronix.de>
CommitterDate: Sat, 10 Aug 2024 10:42:04 +02:00

irqchip/riscv-aplic: Retrigger MSI interrupt on source configuration

The section 4.5.2 of the RISC-V AIA specification says that "any write
to a sourcecfg register of an APLIC might (or might not) cause the
corresponding interrupt-pending bit to be set to one if the rectified
input value is high (= 1) under the new source mode."

When the interrupt type is changed in the sourcecfg register, the APLIC
device might not set the corresponding pending bit, so the interrupt might
never become pending.

To handle sourcecfg register changes for level-triggered interrupts in MSI
mode, manually set the pending bit for retriggering interrupt so it gets
retriggered if it was already asserted.

Fixes: ca8df97fe679 ("irqchip/riscv-aplic: Add support for MSI-mode")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@...ive.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Vincent Chen <vincent.chen@...ive.com>
Reviewed-by: Anup Patel <anup@...infault.org>
Cc: stable@...r.kernel.org
Link: https://lore.kernel.org/all/20240809071049.2454-1-yongxuan.wang@sifive.com
---
 drivers/irqchip/irq-riscv-aplic-msi.c | 32 ++++++++++++++++++++------
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-riscv-aplic-msi.c
index 028444a..d7773f7 100644
--- a/drivers/irqchip/irq-riscv-aplic-msi.c
+++ b/drivers/irqchip/irq-riscv-aplic-msi.c
@@ -32,15 +32,10 @@ static void aplic_msi_irq_unmask(struct irq_data *d)
 	aplic_irq_unmask(d);
 }
 
-static void aplic_msi_irq_eoi(struct irq_data *d)
+static void aplic_msi_irq_retrigger_level(struct irq_data *d)
 {
 	struct aplic_priv *priv = irq_data_get_irq_chip_data(d);
 
-	/*
-	 * EOI handling is required only for level-triggered interrupts
-	 * when APLIC is in MSI mode.
-	 */
-
 	switch (irqd_get_trigger_type(d)) {
 	case IRQ_TYPE_LEVEL_LOW:
 	case IRQ_TYPE_LEVEL_HIGH:
@@ -59,6 +54,29 @@ static void aplic_msi_irq_eoi(struct irq_data *d)
 	}
 }
 
+static void aplic_msi_irq_eoi(struct irq_data *d)
+{
+	/*
+	 * EOI handling is required only for level-triggered interrupts
+	 * when APLIC is in MSI mode.
+	 */
+	aplic_msi_irq_retrigger_level(d);
+}
+
+static int aplic_msi_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	int rc = aplic_irq_set_type(d, type);
+
+	if (rc)
+		return rc;
+	/*
+	 * Updating sourcecfg register for level-triggered interrupts
+	 * requires interrupt retriggering when APLIC is in MSI mode.
+	 */
+	aplic_msi_irq_retrigger_level(d);
+	return 0;
+}
+
 static void aplic_msi_write_msg(struct irq_data *d, struct msi_msg *msg)
 {
 	unsigned int group_index, hart_index, guest_index, val;
@@ -130,7 +148,7 @@ static const struct msi_domain_template aplic_msi_template = {
 		.name			= "APLIC-MSI",
 		.irq_mask		= aplic_msi_irq_mask,
 		.irq_unmask		= aplic_msi_irq_unmask,
-		.irq_set_type		= aplic_irq_set_type,
+		.irq_set_type		= aplic_msi_irq_set_type,
 		.irq_eoi		= aplic_msi_irq_eoi,
 #ifdef CONFIG_SMP
 		.irq_set_affinity	= irq_chip_set_affinity_parent,