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Message-Id: <20240810-b4-mips-ipi-improvements-v3-2-1224fd7c4096@flygoat.com>
Date: Sat, 10 Aug 2024 13:39:07 +0100
From: Jiaxun Yang <jiaxun.yang@...goat.com>
To: Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Florian Fainelli <florian.fainelli@...adcom.com>,
Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
Huacai Chen <chenhuacai@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
Serge Semin <fancer.lancer@...il.com>, Paul Burton <paulburton@...nel.org>
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
Jiaxun Yang <jiaxun.yang@...goat.com>
Subject: [PATCH v3 02/10] MIPS: smp: Manage IPI interrupts as percpu_devid
interrupts
IPI interrupts need to be enabled when a new CPU coming up.
Manage them as percpu_devid interrupts and invoke enable/disable
functions at appropriate time to perform enabling as required,
similar to what RISC-V and Arm doing.
This is required by generic IPI-Mux and some IPI drivers.
Tested-by: Serge Semin <fancer.lancer@...il.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
---
arch/mips/include/asm/ipi.h | 11 +++++++++++
arch/mips/kernel/smp-cps.c | 1 +
arch/mips/kernel/smp.c | 26 ++++++++++++++++++++++++--
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/ipi.h b/arch/mips/include/asm/ipi.h
index df7a0ac4227a..88b507339f51 100644
--- a/arch/mips/include/asm/ipi.h
+++ b/arch/mips/include/asm/ipi.h
@@ -29,6 +29,17 @@ int mips_smp_ipi_allocate(const struct cpumask *mask);
* Return 0 on success.
*/
int mips_smp_ipi_free(const struct cpumask *mask);
+
+void mips_smp_ipi_enable(void);
+void mips_smp_ipi_disable(void);
+#else
+static inline void mips_smp_ipi_enable(void)
+{
+}
+
+static inline void mips_smp_ipi_disable(void)
+{
+}
#endif /* CONFIG_GENERIC_IRQ_IPI */
#endif /* CONFIG_SMP */
#endif
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index b7bcbc4770f2..6845884086f4 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -555,6 +555,7 @@ static int cps_cpu_disable(void)
smp_mb__after_atomic();
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
+ mips_smp_ipi_disable();
irq_migrate_all_off_this_cpu();
return 0;
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 62be2ca9f990..9918bf341ffd 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -186,6 +186,7 @@ irq_handler_t ipi_handlers[IPI_MAX] __read_mostly = {
};
#ifdef CONFIG_GENERIC_IRQ_IPI
+static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev);
static int ipi_virqs[IPI_MAX] __ro_after_init;
static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly;
@@ -225,13 +226,29 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask,
local_irq_restore(flags);
}
+void mips_smp_ipi_enable(void)
+{
+ int i;
+
+ for (i = 0; i < IPI_MAX; i++)
+ enable_percpu_irq(ipi_virqs[i], IRQ_TYPE_NONE);
+}
+
+void mips_smp_ipi_disable(void)
+{
+ int i;
+
+ for (i = 0; i < IPI_MAX; i++)
+ disable_percpu_irq(ipi_virqs[i]);
+}
+
static void smp_ipi_init_one(unsigned int virq, const char *name,
irq_handler_t handler)
{
int ret;
- irq_set_handler(virq, handle_percpu_irq);
- ret = request_irq(virq, handler, IRQF_PERCPU, name, NULL);
+ irq_set_percpu_devid(virq);
+ ret = request_percpu_irq(virq, handler, "IPI", &ipi_dummy_dev);
BUG_ON(ret);
}
@@ -343,6 +360,9 @@ static int __init mips_smp_ipi_init(void)
return -ENODEV;
}
+ /* Enable IPI for Boot CPU */
+ mips_smp_ipi_enable();
+
return 0;
}
early_initcall(mips_smp_ipi_init);
@@ -383,6 +403,8 @@ asmlinkage void start_secondary(void)
synchronise_count_slave(cpu);
+ mips_smp_ipi_enable();
+
/* The CPU is running and counters synchronised, now mark it online */
set_cpu_online(cpu, true);
--
2.46.0
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