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Message-ID: <24e2b1d2c970e894afd8849d501bcddd@manjaro.org>
Date: Sun, 11 Aug 2024 23:39:18 +0200
From: Dragan Simic <dsimic@...jaro.org>
To: Yao Zi <ziyao@...root.org>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>, Greg
Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby
<jirislaby@...nel.org>, Chris Morgan <macromorgan@...mail.com>, Jonas
Karlman <jonas@...boo.se>, Tim Lunn <tim@...thertop.org>, Andy Yan
<andyshrk@....com>, Muhammed Efe Cetin <efectn@...tonmail.com>, Jagan Teki
<jagan@...eble.ai>, Ondrej Jirman <megi@....cz>, Celeste Liu
<CoelacanthusHex@...il.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v2 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC
Hello Yao,
Please see one comment below.
On 2024-08-11 16:07, Yao Zi wrote:
> This initial device tree describes CPU, interrupts and UART on the chip
> and is able to boot into basic kernel with only UART. Cache information
> is omitted for now as there is no precise documentation. Support for
> other features will be added later.
>
> Signed-off-by: Yao Zi <ziyao@...root.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3528.dtsi | 182 +++++++++++++++++++++++
> 1 file changed, 182 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> new file mode 100644
> index 000000000000..0596cdc38737
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2024 Yao Zi <ziyao@...root.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "rockchip,rk3528";
> +
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + serial6 = &uart6;
> + serial7 = &uart7;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + device_type = "cpu";
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + xin24m: clk-24m {
Please use "xin24m: clock-xin24m { ... }" instead, because that follows
the recently established revised pattern for clock names. We should
have
come consistency in the new SoC dtsi additions.
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xin24m";
> + #clock-cells = <0>;
> + };
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